Stephen Boyd b46c0f7465 ARM: 7321/1: cache-v7: Disable preemption when reading CCSIDR ... armv7's flush_cache_all() flushes caches via set/way. To determine the cache attributes (line size, number of sets, etc.) the assembly first writes the CSSELR register to select a cache level and then reads the CCSIDR register. The CSSELR register is banked per-cpu and is used to determine which cache level CCSIDR reads. If the task is migrated between when the CSSELR is written and the CCSIDR is read the CCSIDR value may be for an unexpected cache level (for example L1 instead of L2) and incorrect cache flushing could occur. Disable interrupts across the write and read so that the correct cache attributes are read and used for the cache flushing routine. We disable interrupts instead of disabling preemption because the critical section is only 3 instructions and we want to call v7_dcache_flush_all from __v7_setup which doesn't have a full kernel stack with a struct thread_info. This fixes a problem we see in scm_call() when flush_cache_all() is called from preemptible context and sometimes the L2 cache is not properly flushed out. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Reviewed-by: Nicolas Pitre <nico@linaro.org> Cc: stable@vger.kernel.org Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>		2012-02-09 16:25:37 +00:00
..
abort-ev4.S
abort-ev4t.S
abort-ev5t.S
abort-ev5tj.S
abort-ev6.S
abort-ev7.S
abort-lv4t.S
abort-macro.S
abort-nommu.S
alignment.c
cache-fa.S
cache-feroceon-l2.c
cache-l2x0.c
cache-tauros2.c
cache-v3.S
cache-v4.S
cache-v4wb.S
cache-v4wt.S
cache-v6.S
cache-v7.S	ARM: 7321/1: cache-v7: Disable preemption when reading CCSIDR	2012-02-09 16:25:37 +00:00
cache-xsc3l2.c
context.c
copypage-fa.c
copypage-feroceon.c
copypage-v3.c
copypage-v4mc.c
copypage-v4wb.c
copypage-v4wt.c
copypage-v6.c
copypage-xsc3.c
copypage-xscale.c
dma-mapping.c
extable.c
fault-armv.c
fault.c
fault.h
flush.c
fsr-2level.c
fsr-3level.c
highmem.c
idmap.c
init.c	ARM: fix a section mismatch warning with our use of memblock	2012-01-19 17:26:29 +00:00
iomap.c
ioremap.c	Revert "ARM: 7304/1: ioremap: fix boundary check when reusing static mapping"	2012-02-02 17:37:41 +00:00
Kconfig	ARM: 7291/1: cache: assume 64-byte L1 cachelines for ARMv7 CPUs	2012-01-23 10:20:05 +00:00
Makefile
mm.h
mmap.c
mmu.c
nommu.c
pabort-legacy.S
pabort-v6.S
pabort-v7.S
pgd.c
proc-arm6_7.S
proc-arm7tdmi.S
proc-arm9tdmi.S
proc-arm720.S
proc-arm740.S
proc-arm920.S
proc-arm922.S
proc-arm925.S
proc-arm926.S
proc-arm940.S
proc-arm946.S
proc-arm1020.S
proc-arm1020e.S
proc-arm1022.S
proc-arm1026.S
proc-fa526.S
proc-feroceon.S
proc-macros.S
proc-mohawk.S
proc-sa110.S
proc-sa1100.S
proc-syms.c
proc-v6.S
proc-v7-2level.S
proc-v7-3level.S
proc-v7.S	ARM: 7296/1: proc-v7.S: remove HARVARD_CACHE preprocessor guards	2012-01-23 10:20:06 +00:00
proc-xsc3.S
proc-xscale.S
tlb-fa.S
tlb-v3.S
tlb-v4.S
tlb-v4wb.S
tlb-v4wbi.S
tlb-v6.S
tlb-v7.S
vmregion.c
vmregion.h