forked from luck/tmp_suning_uos_patched
7d24f0b8a5
This patch, however, should be applied on top of the 64k-page-size patch to
fix some problems with hugepage (some pre-existing, another introduced by
this patch).
The patch fixes a bug in the SLB miss handler for hugepages on ppc64
introduced by the dynamic hugepage patch (commit id
c594adad56) due to a misunderstanding of the
srd instruction's behaviour (mea culpa). The problem arises when a 64-bit
process maps some hugepages in the low 4GB of the address space (unusual).
In this case, as well as the 256M segment in question being marked for
hugepages, other segments at 32G intervals will be incorrectly marked for
hugepages.
In the process, this patch tweaks the semantics of the hugepage bitmaps to
be more sensible. Previously, an address below 4G was marked for hugepages
if the appropriate segment bit in the "low areas" bitmask was set *or* if
the low bit in the "high areas" bitmap was set (which would mark all
addresses below 1TB for hugepage). With this patch, any given address is
governed by a single bitmap. Addresses below 4GB are marked for hugepage
if and only if their bit is set in the "low areas" bitmap (256M
granularity). Addresses between 4GB and 1TB are marked for hugepage iff
the low bit in the "high areas" bitmap is set. Higher addresses are marked
for hugepage iff their bit in the "high areas" bitmap is set (1TB
granularity).
To avoid conflicts, this patch must be applied on top of BenH's pending
patch for 64k base page size [0]. As such, this patch also addresses a
hugepage problem introduced by that patch. That patch allows hugepages of
1MB in size on hardware which supports it, however, that won't work when
using 4k pages (4 level pagetable), because in that case hugepage PTEs are
stored at the PMD level, and each PMD entry maps 2MB. This patch simply
disallows hugepages in that case (we can do something cleverer to re-enable
them some other day).
Built, booted, and a handful of hugepage related tests passed on POWER5
LPAR (both ARCH=powerpc and ARCH=ppc64).
[0] http://gate.crashing.org/~benh/ppc64-64k-pages.diff
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Cc: Paul Mackerras <paulus@samba.org>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
91 lines
3.4 KiB
C
91 lines
3.4 KiB
C
#include <asm-generic/pgtable-nopud.h>
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#define PTE_INDEX_SIZE 12
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#define PMD_INDEX_SIZE 12
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#define PUD_INDEX_SIZE 0
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#define PGD_INDEX_SIZE 4
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#define PTE_TABLE_SIZE (sizeof(real_pte_t) << PTE_INDEX_SIZE)
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#define PMD_TABLE_SIZE (sizeof(pmd_t) << PMD_INDEX_SIZE)
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#define PGD_TABLE_SIZE (sizeof(pgd_t) << PGD_INDEX_SIZE)
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#define PTRS_PER_PTE (1 << PTE_INDEX_SIZE)
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#define PTRS_PER_PMD (1 << PMD_INDEX_SIZE)
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#define PTRS_PER_PGD (1 << PGD_INDEX_SIZE)
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/* With 4k base page size, hugepage PTEs go at the PMD level */
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#define MIN_HUGEPTE_SHIFT PAGE_SHIFT
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/* PMD_SHIFT determines what a second-level page table entry can map */
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#define PMD_SHIFT (PAGE_SHIFT + PTE_INDEX_SIZE)
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#define PMD_SIZE (1UL << PMD_SHIFT)
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#define PMD_MASK (~(PMD_SIZE-1))
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/* PGDIR_SHIFT determines what a third-level page table entry can map */
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#define PGDIR_SHIFT (PMD_SHIFT + PMD_INDEX_SIZE)
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#define PGDIR_SIZE (1UL << PGDIR_SHIFT)
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#define PGDIR_MASK (~(PGDIR_SIZE-1))
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/* Additional PTE bits (don't change without checking asm in hash_low.S) */
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#define _PAGE_HPTE_SUB 0x0ffff000 /* combo only: sub pages HPTE bits */
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#define _PAGE_HPTE_SUB0 0x08000000 /* combo only: first sub page */
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#define _PAGE_COMBO 0x10000000 /* this is a combo 4k page */
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#define _PAGE_F_SECOND 0x00008000 /* full page: hidx bits */
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#define _PAGE_F_GIX 0x00007000 /* full page: hidx bits */
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/* PTE flags to conserve for HPTE identification */
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#define _PAGE_HPTEFLAGS (_PAGE_BUSY | _PAGE_HASHPTE | _PAGE_HPTE_SUB |\
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_PAGE_COMBO)
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/* Shift to put page number into pte.
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*
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* That gives us a max RPN of 32 bits, which means a max of 48 bits
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* of addressable physical space.
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* We could get 3 more bits here by setting PTE_RPN_SHIFT to 29 but
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* 32 makes PTEs more readable for debugging for now :)
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*/
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#define PTE_RPN_SHIFT (32)
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#define PTE_RPN_MAX (1UL << (64 - PTE_RPN_SHIFT))
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#define PTE_RPN_MASK (~((1UL<<PTE_RPN_SHIFT)-1))
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/* _PAGE_CHG_MASK masks of bits that are to be preserved accross
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* pgprot changes
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*/
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#define _PAGE_CHG_MASK (PTE_RPN_MASK | _PAGE_HPTEFLAGS | _PAGE_DIRTY | \
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_PAGE_ACCESSED)
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/* Bits to mask out from a PMD to get to the PTE page */
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#define PMD_MASKED_BITS 0x1ff
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/* Bits to mask out from a PGD/PUD to get to the PMD page */
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#define PUD_MASKED_BITS 0x1ff
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#ifndef __ASSEMBLY__
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/* Manipulate "rpte" values */
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#define __real_pte(e,p) ((real_pte_t) { \
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(e), pte_val(*((p) + PTRS_PER_PTE)) })
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#define __rpte_to_hidx(r,index) ((pte_val((r).pte) & _PAGE_COMBO) ? \
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(((r).hidx >> ((index)<<2)) & 0xf) : ((pte_val((r).pte) >> 12) & 0xf))
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#define __rpte_to_pte(r) ((r).pte)
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#define __rpte_sub_valid(rpte, index) \
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(pte_val(rpte.pte) & (_PAGE_HPTE_SUB0 >> (index)))
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/* Trick: we set __end to va + 64k, which happens works for
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* a 16M page as well as we want only one iteration
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*/
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#define pte_iterate_hashed_subpages(rpte, psize, va, index, shift) \
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do { \
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unsigned long __end = va + PAGE_SIZE; \
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unsigned __split = (psize == MMU_PAGE_4K || \
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psize == MMU_PAGE_64K_AP); \
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shift = mmu_psize_defs[psize].shift; \
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for (index = 0; va < __end; index++, va += (1 << shift)) { \
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if (!__split || __rpte_sub_valid(rpte, index)) do { \
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#define pte_iterate_hashed_end() } while(0); } } while(0)
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#endif /* __ASSEMBLY__ */
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