forked from luck/tmp_suning_uos_patched
12eaa328f9
This is where the virtual address of the fault status area belongs. To set it up we don't make a hypervisor call, instead we call OBP's SUNW,set-trap-table with the real address of the fault status area as the second argument. And right before that call we write the virtual address into ASI_SCRATCHPAD vaddr 0x0. Signed-off-by: David S. Miller <davem@davemloft.net>
430 lines
9.3 KiB
ArmAsm
430 lines
9.3 KiB
ArmAsm
/* $Id: trampoline.S,v 1.26 2002/02/09 19:49:30 davem Exp $
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* trampoline.S: Jump start slave processors on sparc64.
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*
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* Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu)
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*/
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#include <asm/head.h>
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#include <asm/asi.h>
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#include <asm/lsu.h>
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#include <asm/dcr.h>
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#include <asm/dcu.h>
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#include <asm/pstate.h>
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#include <asm/page.h>
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#include <asm/pgtable.h>
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#include <asm/spitfire.h>
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#include <asm/processor.h>
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#include <asm/thread_info.h>
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#include <asm/mmu.h>
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#include <asm/hypervisor.h>
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.data
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.align 8
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call_method:
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.asciz "call-method"
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.align 8
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itlb_load:
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.asciz "SUNW,itlb-load"
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.align 8
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dtlb_load:
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.asciz "SUNW,dtlb-load"
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.text
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.align 8
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.globl sparc64_cpu_startup, sparc64_cpu_startup_end
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sparc64_cpu_startup:
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flushw
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BRANCH_IF_SUN4V(g1, niagara_startup)
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BRANCH_IF_CHEETAH_BASE(g1, g5, cheetah_startup)
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BRANCH_IF_CHEETAH_PLUS_OR_FOLLOWON(g1, g5, cheetah_plus_startup)
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ba,pt %xcc, spitfire_startup
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nop
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cheetah_plus_startup:
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/* Preserve OBP chosen DCU and DCR register settings. */
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ba,pt %xcc, cheetah_generic_startup
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nop
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cheetah_startup:
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mov DCR_BPE | DCR_RPE | DCR_SI | DCR_IFPOE | DCR_MS, %g1
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wr %g1, %asr18
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sethi %uhi(DCU_ME|DCU_RE|DCU_HPE|DCU_SPE|DCU_SL|DCU_WE), %g5
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or %g5, %ulo(DCU_ME|DCU_RE|DCU_HPE|DCU_SPE|DCU_SL|DCU_WE), %g5
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sllx %g5, 32, %g5
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or %g5, DCU_DM | DCU_IM | DCU_DC | DCU_IC, %g5
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stxa %g5, [%g0] ASI_DCU_CONTROL_REG
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membar #Sync
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cheetah_generic_startup:
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mov TSB_EXTENSION_P, %g3
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stxa %g0, [%g3] ASI_DMMU
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stxa %g0, [%g3] ASI_IMMU
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membar #Sync
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mov TSB_EXTENSION_S, %g3
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stxa %g0, [%g3] ASI_DMMU
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membar #Sync
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mov TSB_EXTENSION_N, %g3
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stxa %g0, [%g3] ASI_DMMU
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stxa %g0, [%g3] ASI_IMMU
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membar #Sync
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/* fallthru */
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niagara_startup:
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/* Disable STICK_INT interrupts. */
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sethi %hi(0x80000000), %g5
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sllx %g5, 32, %g5
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wr %g5, %asr25
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ba,pt %xcc, startup_continue
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nop
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spitfire_startup:
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mov (LSU_CONTROL_IC | LSU_CONTROL_DC | LSU_CONTROL_IM | LSU_CONTROL_DM), %g1
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stxa %g1, [%g0] ASI_LSU_CONTROL
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membar #Sync
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startup_continue:
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wrpr %g0, 15, %pil
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sethi %hi(0x80000000), %g2
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sllx %g2, 32, %g2
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wr %g2, 0, %tick_cmpr
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BRANCH_IF_SUN4V(g1, niagara_lock_tlb)
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/* Call OBP by hand to lock KERNBASE into i/d tlbs.
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* We lock 2 consequetive entries if we are 'bigkernel'.
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*/
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mov %o0, %l0
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sethi %hi(prom_entry_lock), %g2
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1: ldstub [%g2 + %lo(prom_entry_lock)], %g1
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membar #StoreLoad | #StoreStore
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brnz,pn %g1, 1b
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nop
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sethi %hi(p1275buf), %g2
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or %g2, %lo(p1275buf), %g2
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ldx [%g2 + 0x10], %l2
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mov %sp, %l1
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add %l2, -(192 + 128), %sp
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flushw
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sethi %hi(call_method), %g2
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or %g2, %lo(call_method), %g2
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stx %g2, [%sp + 2047 + 128 + 0x00]
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mov 5, %g2
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stx %g2, [%sp + 2047 + 128 + 0x08]
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mov 1, %g2
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stx %g2, [%sp + 2047 + 128 + 0x10]
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sethi %hi(itlb_load), %g2
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or %g2, %lo(itlb_load), %g2
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stx %g2, [%sp + 2047 + 128 + 0x18]
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sethi %hi(prom_mmu_ihandle_cache), %g2
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lduw [%g2 + %lo(prom_mmu_ihandle_cache)], %g2
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stx %g2, [%sp + 2047 + 128 + 0x20]
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sethi %hi(KERNBASE), %g2
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stx %g2, [%sp + 2047 + 128 + 0x28]
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sethi %hi(kern_locked_tte_data), %g2
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ldx [%g2 + %lo(kern_locked_tte_data)], %g2
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stx %g2, [%sp + 2047 + 128 + 0x30]
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mov 15, %g2
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BRANCH_IF_ANY_CHEETAH(g1,g5,1f)
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mov 63, %g2
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1:
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stx %g2, [%sp + 2047 + 128 + 0x38]
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sethi %hi(p1275buf), %g2
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or %g2, %lo(p1275buf), %g2
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ldx [%g2 + 0x08], %o1
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call %o1
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add %sp, (2047 + 128), %o0
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sethi %hi(bigkernel), %g2
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lduw [%g2 + %lo(bigkernel)], %g2
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brz,pt %g2, do_dtlb
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nop
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sethi %hi(call_method), %g2
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or %g2, %lo(call_method), %g2
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stx %g2, [%sp + 2047 + 128 + 0x00]
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mov 5, %g2
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stx %g2, [%sp + 2047 + 128 + 0x08]
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mov 1, %g2
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stx %g2, [%sp + 2047 + 128 + 0x10]
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sethi %hi(itlb_load), %g2
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or %g2, %lo(itlb_load), %g2
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stx %g2, [%sp + 2047 + 128 + 0x18]
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sethi %hi(prom_mmu_ihandle_cache), %g2
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lduw [%g2 + %lo(prom_mmu_ihandle_cache)], %g2
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stx %g2, [%sp + 2047 + 128 + 0x20]
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sethi %hi(KERNBASE + 0x400000), %g2
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stx %g2, [%sp + 2047 + 128 + 0x28]
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sethi %hi(kern_locked_tte_data), %g2
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ldx [%g2 + %lo(kern_locked_tte_data)], %g2
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sethi %hi(0x400000), %g1
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add %g2, %g1, %g2
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stx %g2, [%sp + 2047 + 128 + 0x30]
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mov 14, %g2
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BRANCH_IF_ANY_CHEETAH(g1,g5,1f)
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mov 62, %g2
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1:
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stx %g2, [%sp + 2047 + 128 + 0x38]
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sethi %hi(p1275buf), %g2
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or %g2, %lo(p1275buf), %g2
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ldx [%g2 + 0x08], %o1
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call %o1
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add %sp, (2047 + 128), %o0
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do_dtlb:
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sethi %hi(call_method), %g2
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or %g2, %lo(call_method), %g2
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stx %g2, [%sp + 2047 + 128 + 0x00]
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mov 5, %g2
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stx %g2, [%sp + 2047 + 128 + 0x08]
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mov 1, %g2
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stx %g2, [%sp + 2047 + 128 + 0x10]
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sethi %hi(dtlb_load), %g2
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or %g2, %lo(dtlb_load), %g2
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stx %g2, [%sp + 2047 + 128 + 0x18]
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sethi %hi(prom_mmu_ihandle_cache), %g2
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lduw [%g2 + %lo(prom_mmu_ihandle_cache)], %g2
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stx %g2, [%sp + 2047 + 128 + 0x20]
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sethi %hi(KERNBASE), %g2
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stx %g2, [%sp + 2047 + 128 + 0x28]
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sethi %hi(kern_locked_tte_data), %g2
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ldx [%g2 + %lo(kern_locked_tte_data)], %g2
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stx %g2, [%sp + 2047 + 128 + 0x30]
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mov 15, %g2
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BRANCH_IF_ANY_CHEETAH(g1,g5,1f)
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mov 63, %g2
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1:
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stx %g2, [%sp + 2047 + 128 + 0x38]
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sethi %hi(p1275buf), %g2
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or %g2, %lo(p1275buf), %g2
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ldx [%g2 + 0x08], %o1
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call %o1
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add %sp, (2047 + 128), %o0
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sethi %hi(bigkernel), %g2
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lduw [%g2 + %lo(bigkernel)], %g2
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brz,pt %g2, do_unlock
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nop
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sethi %hi(call_method), %g2
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or %g2, %lo(call_method), %g2
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stx %g2, [%sp + 2047 + 128 + 0x00]
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mov 5, %g2
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stx %g2, [%sp + 2047 + 128 + 0x08]
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mov 1, %g2
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stx %g2, [%sp + 2047 + 128 + 0x10]
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sethi %hi(dtlb_load), %g2
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or %g2, %lo(dtlb_load), %g2
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stx %g2, [%sp + 2047 + 128 + 0x18]
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sethi %hi(prom_mmu_ihandle_cache), %g2
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lduw [%g2 + %lo(prom_mmu_ihandle_cache)], %g2
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stx %g2, [%sp + 2047 + 128 + 0x20]
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sethi %hi(KERNBASE + 0x400000), %g2
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stx %g2, [%sp + 2047 + 128 + 0x28]
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sethi %hi(kern_locked_tte_data), %g2
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ldx [%g2 + %lo(kern_locked_tte_data)], %g2
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sethi %hi(0x400000), %g1
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add %g2, %g1, %g2
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stx %g2, [%sp + 2047 + 128 + 0x30]
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mov 14, %g2
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BRANCH_IF_ANY_CHEETAH(g1,g5,1f)
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mov 62, %g2
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1:
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stx %g2, [%sp + 2047 + 128 + 0x38]
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sethi %hi(p1275buf), %g2
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or %g2, %lo(p1275buf), %g2
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ldx [%g2 + 0x08], %o1
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call %o1
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add %sp, (2047 + 128), %o0
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do_unlock:
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sethi %hi(prom_entry_lock), %g2
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stb %g0, [%g2 + %lo(prom_entry_lock)]
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membar #StoreStore | #StoreLoad
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ba,pt %xcc, after_lock_tlb
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nop
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niagara_lock_tlb:
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mov HV_FAST_MMU_MAP_PERM_ADDR, %o5
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sethi %hi(KERNBASE), %o0
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clr %o1
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sethi %hi(kern_locked_tte_data), %o2
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ldx [%o2 + %lo(kern_locked_tte_data)], %o2
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mov HV_MMU_IMMU, %o3
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ta HV_FAST_TRAP
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mov HV_FAST_MMU_MAP_PERM_ADDR, %o5
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sethi %hi(KERNBASE), %o0
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clr %o1
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sethi %hi(kern_locked_tte_data), %o2
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ldx [%o2 + %lo(kern_locked_tte_data)], %o2
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mov HV_MMU_DMMU, %o3
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ta HV_FAST_TRAP
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sethi %hi(bigkernel), %g2
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lduw [%g2 + %lo(bigkernel)], %g2
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brz,pt %g2, after_lock_tlb
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nop
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mov HV_FAST_MMU_MAP_PERM_ADDR, %o5
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sethi %hi(KERNBASE + 0x400000), %o0
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clr %o1
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sethi %hi(kern_locked_tte_data), %o2
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ldx [%o2 + %lo(kern_locked_tte_data)], %o2
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sethi %hi(0x400000), %o3
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add %o2, %o3, %o2
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mov HV_MMU_IMMU, %o3
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ta HV_FAST_TRAP
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mov HV_FAST_MMU_MAP_PERM_ADDR, %o5
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sethi %hi(KERNBASE + 0x400000), %o0
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clr %o1
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sethi %hi(kern_locked_tte_data), %o2
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ldx [%o2 + %lo(kern_locked_tte_data)], %o2
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sethi %hi(0x400000), %o3
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add %o2, %o3, %o2
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mov HV_MMU_DMMU, %o3
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ta HV_FAST_TRAP
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after_lock_tlb:
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mov %l1, %sp
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flushw
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mov %l0, %o0
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wrpr %g0, (PSTATE_PRIV | PSTATE_PEF), %pstate
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wr %g0, 0, %fprs
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/* XXX Buggy PROM... */
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srl %o0, 0, %o0
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ldx [%o0], %g6
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wr %g0, ASI_P, %asi
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mov PRIMARY_CONTEXT, %g7
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661: stxa %g0, [%g7] ASI_DMMU
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.section .sun4v_1insn_patch, "ax"
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.word 661b
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stxa %g0, [%g7] ASI_MMU
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.previous
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membar #Sync
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mov SECONDARY_CONTEXT, %g7
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661: stxa %g0, [%g7] ASI_DMMU
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.section .sun4v_1insn_patch, "ax"
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.word 661b
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stxa %g0, [%g7] ASI_MMU
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.previous
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membar #Sync
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mov 1, %g5
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sllx %g5, THREAD_SHIFT, %g5
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sub %g5, (STACKFRAME_SZ + STACK_BIAS), %g5
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add %g6, %g5, %sp
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mov 0, %fp
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wrpr %g0, 0, %wstate
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wrpr %g0, 0, %tl
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/* Load TBA, then we can resurface. */
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sethi %hi(sparc64_ttable_tl0), %g5
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wrpr %g5, %tba
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ldx [%g6 + TI_TASK], %g4
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wrpr %g0, 0, %wstate
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call init_irqwork_curcpu
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nop
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sethi %hi(tlb_type), %g3
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lduw [%g3 + %lo(tlb_type)], %g2
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cmp %g2, 3
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bne,pt %icc, 1f
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nop
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call sun4v_init_mondo_queues
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nop
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1: call init_cur_cpu_trap
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nop
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/* Start using proper page size encodings in ctx register. */
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sethi %hi(sparc64_kern_pri_context), %g3
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ldx [%g3 + %lo(sparc64_kern_pri_context)], %g2
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mov PRIMARY_CONTEXT, %g1
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661: stxa %g2, [%g1] ASI_DMMU
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.section .sun4v_1insn_patch, "ax"
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.word 661b
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stxa %g2, [%g1] ASI_MMU
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.previous
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membar #Sync
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rdpr %pstate, %o1
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or %o1, PSTATE_IE, %o1
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wrpr %o1, 0, %pstate
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sethi %hi(is_sun4v), %o0
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lduw [%o0 + %lo(is_sun4v)], %o0
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brz,pt %o0, 1f
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nop
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TRAP_LOAD_TRAP_BLOCK(%g2, %g3)
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add %g2, TRAP_PER_CPU_FAULT_INFO, %g2
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stxa %g2, [%g0] ASI_SCRATCHPAD
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/* Compute physical address:
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*
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* paddr = kern_base + (mmfsa_vaddr - KERNBASE)
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*/
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sethi %hi(KERNBASE), %g3
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sub %g2, %g3, %g2
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sethi %hi(kern_base), %g3
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ldx [%g3 + %lo(kern_base)], %g3
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add %g2, %g3, %o1
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call prom_set_trap_table_sun4v
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sethi %hi(sparc64_ttable_tl0), %o0
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ba,pt %xcc, 2f
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nop
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1: call prom_set_trap_table
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sethi %hi(sparc64_ttable_tl0), %o0
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2: call smp_callin
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nop
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call cpu_idle
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mov 0, %o0
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call cpu_panic
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nop
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1: b,a,pt %xcc, 1b
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.align 8
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sparc64_cpu_startup_end:
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