forked from luck/tmp_suning_uos_patched
156 lines
3.9 KiB
ArmAsm
156 lines
3.9 KiB
ArmAsm
/*
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* Carsten Langgaard, carstenl@mips.com
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* Copyright (C) 1999, 2000 MIPS Technologies, Inc. All rights reserved.
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*
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* ########################################################################
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*
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* This program is free software; you can distribute it and/or modify it
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* under the terms of the GNU General Public License (Version 2) as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
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*
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* ########################################################################
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*
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* Interrupt exception dispatch code.
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*
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*/
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#include <linux/config.h>
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#include <asm/asm.h>
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#include <asm/mipsregs.h>
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#include <asm/regdef.h>
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#include <asm/stackframe.h>
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#ifdef CONFIG_MIPS_ATLAS
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#include <asm/mips-boards/atlasint.h>
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#define CASCADE_IRQ MIPSCPU_INT_ATLAS
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#define CASCADE_DISPATCH atlas_hw0_irqdispatch
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#endif
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#ifdef CONFIG_MIPS_MALTA
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#include <asm/mips-boards/maltaint.h>
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#define CASCADE_IRQ MIPSCPU_INT_I8259A
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#define CASCADE_DISPATCH malta_hw0_irqdispatch
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#endif
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#ifdef CONFIG_MIPS_SEAD
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#include <asm/mips-boards/seadint.h>
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#endif
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/* A lot of complication here is taken away because:
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*
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* 1) We handle one interrupt and return, sitting in a loop and moving across
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* all the pending IRQ bits in the cause register is _NOT_ the answer, the
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* common case is one pending IRQ so optimize in that direction.
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*
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* 2) We need not check against bits in the status register IRQ mask, that
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* would make this routine slow as hell.
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*
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* 3) Linux only thinks in terms of all IRQs on or all IRQs off, nothing in
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* between like BSD spl() brain-damage.
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*
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* Furthermore, the IRQs on the MIPS board look basically (barring software
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* IRQs which we don't use at all and all external interrupt sources are
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* combined together on hardware interrupt 0 (MIPS IRQ 2)) like:
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*
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* MIPS IRQ Source
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* -------- ------
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* 0 Software (ignored)
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* 1 Software (ignored)
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* 2 Combined hardware interrupt (hw0)
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* 3 Hardware (ignored)
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* 4 Hardware (ignored)
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* 5 Hardware (ignored)
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* 6 Hardware (ignored)
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* 7 R4k timer (what we use)
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*
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* Note: On the SEAD board thing are a little bit different.
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* Here IRQ 2 (hw0) is wired to the UART0 and IRQ 3 (hw1) is wired
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* wired to UART1.
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*
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* We handle the IRQ according to _our_ priority which is:
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*
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* Highest ---- R4k Timer
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* Lowest ---- Combined hardware interrupt
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*
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* then we just return, if multiple IRQs are pending then we will just take
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* another exception, big deal.
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*/
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.text
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.set noreorder
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.set noat
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.align 5
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NESTED(mipsIRQ, PT_SIZE, sp)
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SAVE_ALL
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CLI
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.set at
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mfc0 s0, CP0_CAUSE # get irq bits
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mfc0 s1, CP0_STATUS # get irq mask
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andi s0, ST0_IM # CAUSE.CE may be non-zero!
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and s0, s1
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#if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64)
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.set mips32
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clz a0, s0
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.set mips0
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negu a0
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addu a0, 31-CAUSEB_IP
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bltz a0, spurious
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#else
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beqz s0, spurious
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li a0, 7
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and t0, s0, 0xf000
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sltiu t0, t0, 1
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sll t0, 2
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subu a0, t0
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sll s0, t0
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and t0, s0, 0xc000
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sltiu t0, t0, 1
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sll t0, 1
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subu a0, t0
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sll s0, t0
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and t0, s0, 0x8000
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sltiu t0, t0, 1
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# sll t0, 0
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subu a0, t0
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# sll s0, t0
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#endif
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#ifdef CASCADE_IRQ
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li a1, CASCADE_IRQ
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bne a0, a1, 1f
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addu a0, MIPSCPU_INT_BASE
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jal CASCADE_DISPATCH
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move a0, sp
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j ret_from_irq
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nop
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1:
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#else
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addu a0, MIPSCPU_INT_BASE
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#endif
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jal do_IRQ
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move a1, sp
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j ret_from_irq
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nop
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spurious:
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j spurious_interrupt
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nop
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END(mipsIRQ)
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