forked from luck/tmp_suning_uos_patched
122 lines
3.2 KiB
C
122 lines
3.2 KiB
C
/*
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* Copyright (C) 2013 Imagination Technologies
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* Author: Paul Burton <paul.burton@imgtec.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#include <linux/errno.h>
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#include <asm/mips-cm.h>
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#include <asm/mipsregs.h>
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void __iomem *mips_cm_base;
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void __iomem *mips_cm_l2sync_base;
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phys_addr_t __mips_cm_phys_base(void)
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{
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u32 config3 = read_c0_config3();
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u32 cmgcr;
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/* Check the CMGCRBase register is implemented */
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if (!(config3 & MIPS_CONF3_CMGCR))
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return 0;
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/* Read the address from CMGCRBase */
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cmgcr = read_c0_cmgcrbase();
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return (cmgcr & MIPS_CMGCRF_BASE) << (36 - 32);
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}
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phys_addr_t mips_cm_phys_base(void)
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__attribute__((weak, alias("__mips_cm_phys_base")));
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phys_addr_t __mips_cm_l2sync_phys_base(void)
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{
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u32 base_reg;
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/*
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* If the L2-only sync region is already enabled then leave it at it's
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* current location.
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*/
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base_reg = read_gcr_l2_only_sync_base();
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if (base_reg & CM_GCR_L2_ONLY_SYNC_BASE_SYNCEN_MSK)
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return base_reg & CM_GCR_L2_ONLY_SYNC_BASE_SYNCBASE_MSK;
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/* Default to following the CM */
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return mips_cm_phys_base() + MIPS_CM_GCR_SIZE;
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}
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phys_addr_t mips_cm_l2sync_phys_base(void)
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__attribute__((weak, alias("__mips_cm_l2sync_phys_base")));
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static void mips_cm_probe_l2sync(void)
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{
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unsigned major_rev;
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phys_addr_t addr;
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/* L2-only sync was introduced with CM major revision 6 */
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major_rev = (read_gcr_rev() & CM_GCR_REV_MAJOR_MSK) >>
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CM_GCR_REV_MAJOR_SHF;
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if (major_rev < 6)
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return;
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/* Find a location for the L2 sync region */
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addr = mips_cm_l2sync_phys_base();
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BUG_ON((addr & CM_GCR_L2_ONLY_SYNC_BASE_SYNCBASE_MSK) != addr);
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if (!addr)
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return;
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/* Set the region base address & enable it */
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write_gcr_l2_only_sync_base(addr | CM_GCR_L2_ONLY_SYNC_BASE_SYNCEN_MSK);
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/* Map the region */
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mips_cm_l2sync_base = ioremap_nocache(addr, MIPS_CM_L2SYNC_SIZE);
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}
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int mips_cm_probe(void)
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{
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phys_addr_t addr;
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u32 base_reg;
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addr = mips_cm_phys_base();
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BUG_ON((addr & CM_GCR_BASE_GCRBASE_MSK) != addr);
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if (!addr)
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return -ENODEV;
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mips_cm_base = ioremap_nocache(addr, MIPS_CM_GCR_SIZE);
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if (!mips_cm_base)
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return -ENXIO;
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/* sanity check that we're looking at a CM */
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base_reg = read_gcr_base();
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if ((base_reg & CM_GCR_BASE_GCRBASE_MSK) != addr) {
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pr_err("GCRs appear to have been moved (expected them at 0x%08lx)!\n",
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(unsigned long)addr);
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mips_cm_base = NULL;
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return -ENODEV;
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}
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/* set default target to memory */
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base_reg &= ~CM_GCR_BASE_CMDEFTGT_MSK;
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base_reg |= CM_GCR_BASE_CMDEFTGT_MEM;
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write_gcr_base(base_reg);
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/* disable CM regions */
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write_gcr_reg0_base(CM_GCR_REGn_BASE_BASEADDR_MSK);
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write_gcr_reg0_mask(CM_GCR_REGn_MASK_ADDRMASK_MSK);
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write_gcr_reg1_base(CM_GCR_REGn_BASE_BASEADDR_MSK);
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write_gcr_reg1_mask(CM_GCR_REGn_MASK_ADDRMASK_MSK);
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write_gcr_reg2_base(CM_GCR_REGn_BASE_BASEADDR_MSK);
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write_gcr_reg2_mask(CM_GCR_REGn_MASK_ADDRMASK_MSK);
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write_gcr_reg3_base(CM_GCR_REGn_BASE_BASEADDR_MSK);
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write_gcr_reg3_mask(CM_GCR_REGn_MASK_ADDRMASK_MSK);
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/* probe for an L2-only sync region */
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mips_cm_probe_l2sync();
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return 0;
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}
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