forked from luck/tmp_suning_uos_patched
6656920b0b
Add support for processors that have cache-aliasing issues, such as the Stretch S5000 processor. Cache-aliasing means that the size of the cache (for one way) is larger than the page size, thus, a page can end up in several places in cache depending on the virtual to physical translation. The method used here is to map a user page temporarily through the auto-refill way 0 and of of the DTLB. We probably will want to revisit this issue and use a better approach with kmap/kunmap. Signed-off-by: Chris Zankel <chris@zankel.net>
48 lines
1.1 KiB
C
48 lines
1.1 KiB
C
/*
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* include/asm-xtensa/tlb.h
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2001 - 2005 Tensilica Inc.
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*/
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#ifndef _XTENSA_TLB_H
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#define _XTENSA_TLB_H
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#include <asm/cache.h>
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#include <asm/page.h>
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#if (DCACHE_WAY_SIZE <= PAGE_SIZE)
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/* Note, read http://lkml.org/lkml/2004/1/15/6 */
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# define tlb_start_vma(tlb,vma) do { } while (0)
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# define tlb_end_vma(tlb,vma) do { } while (0)
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#else
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# define tlb_start_vma(tlb, vma) \
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do { \
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if (!tlb->fullmm) \
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flush_cache_range(vma, vma->vm_start, vma->vm_end); \
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} while(0)
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# define tlb_end_vma(tlb, vma) \
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do { \
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if (!tlb->fullmm) \
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flush_tlb_range(vma, vma->vm_start, vma->vm_end); \
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} while(0)
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#endif
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#define __tlb_remove_tlb_entry(tlb,pte,addr) do { } while (0)
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#define tlb_flush(tlb) flush_tlb_mm((tlb)->mm)
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#include <asm-generic/tlb.h>
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#define __pte_free_tlb(tlb,pte) pte_free(pte)
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#endif /* _XTENSA_TLB_H */
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