forked from luck/tmp_suning_uos_patched
2874c5fd28
Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license as published by the free software foundation either version 2 of the license or at your option any later version extracted by the scancode license scanner the SPDX license identifier GPL-2.0-or-later has been chosen to replace the boilerplate/reference in 3029 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190527070032.746973796@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
176 lines
5.0 KiB
ArmAsm
176 lines
5.0 KiB
ArmAsm
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* Shared glue code for 128bit block ciphers, AVX2 assembler macros
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*
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* Copyright © 2012-2013 Jussi Kivilinna <jussi.kivilinna@mbnet.fi>
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*/
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#define load_16way(src, x0, x1, x2, x3, x4, x5, x6, x7) \
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vmovdqu (0*32)(src), x0; \
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vmovdqu (1*32)(src), x1; \
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vmovdqu (2*32)(src), x2; \
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vmovdqu (3*32)(src), x3; \
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vmovdqu (4*32)(src), x4; \
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vmovdqu (5*32)(src), x5; \
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vmovdqu (6*32)(src), x6; \
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vmovdqu (7*32)(src), x7;
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#define store_16way(dst, x0, x1, x2, x3, x4, x5, x6, x7) \
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vmovdqu x0, (0*32)(dst); \
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vmovdqu x1, (1*32)(dst); \
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vmovdqu x2, (2*32)(dst); \
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vmovdqu x3, (3*32)(dst); \
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vmovdqu x4, (4*32)(dst); \
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vmovdqu x5, (5*32)(dst); \
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vmovdqu x6, (6*32)(dst); \
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vmovdqu x7, (7*32)(dst);
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#define store_cbc_16way(src, dst, x0, x1, x2, x3, x4, x5, x6, x7, t0) \
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vpxor t0, t0, t0; \
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vinserti128 $1, (src), t0, t0; \
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vpxor t0, x0, x0; \
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vpxor (0*32+16)(src), x1, x1; \
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vpxor (1*32+16)(src), x2, x2; \
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vpxor (2*32+16)(src), x3, x3; \
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vpxor (3*32+16)(src), x4, x4; \
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vpxor (4*32+16)(src), x5, x5; \
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vpxor (5*32+16)(src), x6, x6; \
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vpxor (6*32+16)(src), x7, x7; \
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store_16way(dst, x0, x1, x2, x3, x4, x5, x6, x7);
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#define inc_le128(x, minus_one, tmp) \
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vpcmpeqq minus_one, x, tmp; \
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vpsubq minus_one, x, x; \
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vpslldq $8, tmp, tmp; \
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vpsubq tmp, x, x;
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#define add2_le128(x, minus_one, minus_two, tmp1, tmp2) \
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vpcmpeqq minus_one, x, tmp1; \
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vpcmpeqq minus_two, x, tmp2; \
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vpsubq minus_two, x, x; \
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vpor tmp2, tmp1, tmp1; \
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vpslldq $8, tmp1, tmp1; \
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vpsubq tmp1, x, x;
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#define load_ctr_16way(iv, bswap, x0, x1, x2, x3, x4, x5, x6, x7, t0, t0x, t1, \
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t1x, t2, t2x, t3, t3x, t4, t5) \
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vpcmpeqd t0, t0, t0; \
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vpsrldq $8, t0, t0; /* ab: -1:0 ; cd: -1:0 */ \
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vpaddq t0, t0, t4; /* ab: -2:0 ; cd: -2:0 */\
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\
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/* load IV and byteswap */ \
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vmovdqu (iv), t2x; \
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vmovdqa t2x, t3x; \
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inc_le128(t2x, t0x, t1x); \
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vbroadcasti128 bswap, t1; \
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vinserti128 $1, t2x, t3, t2; /* ab: le0 ; cd: le1 */ \
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vpshufb t1, t2, x0; \
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\
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/* construct IVs */ \
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add2_le128(t2, t0, t4, t3, t5); /* ab: le2 ; cd: le3 */ \
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vpshufb t1, t2, x1; \
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add2_le128(t2, t0, t4, t3, t5); \
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vpshufb t1, t2, x2; \
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add2_le128(t2, t0, t4, t3, t5); \
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vpshufb t1, t2, x3; \
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add2_le128(t2, t0, t4, t3, t5); \
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vpshufb t1, t2, x4; \
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add2_le128(t2, t0, t4, t3, t5); \
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vpshufb t1, t2, x5; \
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add2_le128(t2, t0, t4, t3, t5); \
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vpshufb t1, t2, x6; \
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add2_le128(t2, t0, t4, t3, t5); \
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vpshufb t1, t2, x7; \
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vextracti128 $1, t2, t2x; \
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inc_le128(t2x, t0x, t3x); \
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vmovdqu t2x, (iv);
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#define store_ctr_16way(src, dst, x0, x1, x2, x3, x4, x5, x6, x7) \
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vpxor (0*32)(src), x0, x0; \
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vpxor (1*32)(src), x1, x1; \
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vpxor (2*32)(src), x2, x2; \
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vpxor (3*32)(src), x3, x3; \
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vpxor (4*32)(src), x4, x4; \
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vpxor (5*32)(src), x5, x5; \
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vpxor (6*32)(src), x6, x6; \
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vpxor (7*32)(src), x7, x7; \
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store_16way(dst, x0, x1, x2, x3, x4, x5, x6, x7);
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#define gf128mul_x_ble(iv, mask, tmp) \
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vpsrad $31, iv, tmp; \
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vpaddq iv, iv, iv; \
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vpshufd $0x13, tmp, tmp; \
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vpand mask, tmp, tmp; \
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vpxor tmp, iv, iv;
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#define gf128mul_x2_ble(iv, mask1, mask2, tmp0, tmp1) \
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vpsrad $31, iv, tmp0; \
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vpaddq iv, iv, tmp1; \
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vpsllq $2, iv, iv; \
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vpshufd $0x13, tmp0, tmp0; \
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vpsrad $31, tmp1, tmp1; \
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vpand mask2, tmp0, tmp0; \
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vpshufd $0x13, tmp1, tmp1; \
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vpxor tmp0, iv, iv; \
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vpand mask1, tmp1, tmp1; \
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vpxor tmp1, iv, iv;
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#define load_xts_16way(iv, src, dst, x0, x1, x2, x3, x4, x5, x6, x7, tiv, \
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tivx, t0, t0x, t1, t1x, t2, t2x, t3, \
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xts_gf128mul_and_shl1_mask_0, \
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xts_gf128mul_and_shl1_mask_1) \
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vbroadcasti128 xts_gf128mul_and_shl1_mask_0, t1; \
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\
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/* load IV and construct second IV */ \
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vmovdqu (iv), tivx; \
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vmovdqa tivx, t0x; \
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gf128mul_x_ble(tivx, t1x, t2x); \
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vbroadcasti128 xts_gf128mul_and_shl1_mask_1, t2; \
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vinserti128 $1, tivx, t0, tiv; \
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vpxor (0*32)(src), tiv, x0; \
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vmovdqu tiv, (0*32)(dst); \
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\
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/* construct and store IVs, also xor with source */ \
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gf128mul_x2_ble(tiv, t1, t2, t0, t3); \
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vpxor (1*32)(src), tiv, x1; \
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vmovdqu tiv, (1*32)(dst); \
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\
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gf128mul_x2_ble(tiv, t1, t2, t0, t3); \
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vpxor (2*32)(src), tiv, x2; \
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vmovdqu tiv, (2*32)(dst); \
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\
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gf128mul_x2_ble(tiv, t1, t2, t0, t3); \
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vpxor (3*32)(src), tiv, x3; \
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vmovdqu tiv, (3*32)(dst); \
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\
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gf128mul_x2_ble(tiv, t1, t2, t0, t3); \
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vpxor (4*32)(src), tiv, x4; \
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vmovdqu tiv, (4*32)(dst); \
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\
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gf128mul_x2_ble(tiv, t1, t2, t0, t3); \
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vpxor (5*32)(src), tiv, x5; \
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vmovdqu tiv, (5*32)(dst); \
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\
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gf128mul_x2_ble(tiv, t1, t2, t0, t3); \
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vpxor (6*32)(src), tiv, x6; \
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vmovdqu tiv, (6*32)(dst); \
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\
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gf128mul_x2_ble(tiv, t1, t2, t0, t3); \
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vpxor (7*32)(src), tiv, x7; \
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vmovdqu tiv, (7*32)(dst); \
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\
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vextracti128 $1, tiv, tivx; \
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gf128mul_x_ble(tivx, t1x, t2x); \
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vmovdqu tivx, (iv);
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#define store_xts_16way(dst, x0, x1, x2, x3, x4, x5, x6, x7) \
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vpxor (0*32)(dst), x0, x0; \
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vpxor (1*32)(dst), x1, x1; \
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vpxor (2*32)(dst), x2, x2; \
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vpxor (3*32)(dst), x3, x3; \
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vpxor (4*32)(dst), x4, x4; \
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vpxor (5*32)(dst), x5, x5; \
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vpxor (6*32)(dst), x6, x6; \
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vpxor (7*32)(dst), x7, x7; \
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store_16way(dst, x0, x1, x2, x3, x4, x5, x6, x7);
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