forked from luck/tmp_suning_uos_patched
ab7c01fdc3
There are five MIPS32/64 architecture releases currently available:
from 1 to 6 except fourth one, which was intentionally skipped.
Three of them can be called as major: 1st, 2nd and 6th, that not only
have some system level alterations, but also introduced significant
core/ISA level updates. The rest of the MIPS architecture releases are
minor.
Even though they don't have as much ISA/system/core level changes
as the major ones with respect to the previous releases, they still
provide a set of updates (I'd say they were intended to be the
intermediate releases before a major one) that might be useful for the
kernel and user-level code, when activated by the kernel or compiler.
In particular the following features were introduced or ended up being
available at/after MIPS32/64 Release 5 architecture:
+ the last release of the misaligned memory access instructions,
+ virtualisation - VZ ASE - is optional component of the arch,
+ SIMD - MSA ASE - is optional component of the arch,
+ DSP ASE is optional component of the arch,
+ CP0.Status.FR=1 for CP1.FIR.F64=1 (pure 64-bit FPU general registers)
must be available if FPU is implemented,
+ CP1.FIR.Has2008 support is required so CP1.FCSR.{ABS2008,NAN2008} bits
are available.
+ UFR/UNFR aliases to access CP0.Status.FR from user-space by means of
ctc1/cfc1 instructions (enabled by CP0.Config5.UFR),
+ CP0.COnfig5.LLB=1 and eretnc instruction are implemented to without
accidentally clearing LL-bit when returning from an interrupt,
exception, or error trap,
+ XPA feature together with extended versions of CPx registers is
introduced, which needs to have mfhc0/mthc0 instructions available.
So due to these changes GNU GCC provides an extended instructions set
support for MIPS32/64 Release 5 by default like eretnc/mfhc0/mthc0. Even
though the architecture alteration isn't that big, it still worth to be
taken into account by the kernel software. Finally we can't deny that
some optimization/limitations might be found in future and implemented
on some level in kernel or compiler. In this case having even
intermediate MIPS architecture releases support would be more than
useful.
So the most of the changes provided by this commit can be split into
either compile- or runtime configs related. The compile-time related
changes are caused by adding the new CONFIG_CPU_MIPS32_R5/CONFIG_CPU_MIPSR5
configs and concern the code activating MIPSR2 or MIPSR6 already
implemented features (like eretnc/LLbit, mthc0/mfhc0). In addition
CPU_HAS_MSA can be now freely enabled for MIPS32/64 release 5 based
platforms as this is done for CPU_MIPS32_R6 CPUs. The runtime changes
concerns the features which are handled with respect to the MIPS ISA
revision detected at run-time by means of CP0.Config.{AT,AR} bits. Alas
these fields can be used to detect either r1 or r2 or r6 releases.
But since we know which CPUs in fact support the R5 arch, we can manually
set MIPS_CPU_ISA_M32R5/MIPS_CPU_ISA_M64R5 bit of c->isa_level and then
use cpu_has_mips32r5/cpu_has_mips64r5 where it's appropriate.
Since XPA/EVA provide too complex alterationss and to have them used with
MIPS32 Release 2 charged kernels (for compatibility with current platform
configs) they are left to be setup as a separate kernel configs.
Co-developed-by: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
Signed-off-by: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Cc: Paul Burton <paulburton@kernel.org>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: devicetree@vger.kernel.org
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
187 lines
4.3 KiB
ArmAsm
187 lines
4.3 KiB
ArmAsm
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 1994 - 2000, 2001, 2003 Ralf Baechle
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* Copyright (C) 1999, 2000 Silicon Graphics, Inc.
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* Copyright (C) 2001 MIPS Technologies, Inc.
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*/
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#include <asm/asm.h>
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#include <asm/asmmacro.h>
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#include <asm/compiler.h>
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#include <asm/irqflags.h>
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#include <asm/regdef.h>
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#include <asm/mipsregs.h>
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#include <asm/stackframe.h>
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#include <asm/isadep.h>
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#include <asm/thread_info.h>
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#include <asm/war.h>
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#ifndef CONFIG_PREEMPTION
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#define resume_kernel restore_all
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#else
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#define __ret_from_irq ret_from_exception
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#endif
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.text
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.align 5
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#ifndef CONFIG_PREEMPTION
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FEXPORT(ret_from_exception)
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local_irq_disable # preempt stop
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b __ret_from_irq
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#endif
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FEXPORT(ret_from_irq)
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LONG_S s0, TI_REGS($28)
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FEXPORT(__ret_from_irq)
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/*
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* We can be coming here from a syscall done in the kernel space,
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* e.g. a failed kernel_execve().
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*/
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resume_userspace_check:
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LONG_L t0, PT_STATUS(sp) # returning to kernel mode?
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andi t0, t0, KU_USER
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beqz t0, resume_kernel
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resume_userspace:
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local_irq_disable # make sure we dont miss an
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# interrupt setting need_resched
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# between sampling and return
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LONG_L a2, TI_FLAGS($28) # current->work
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andi t0, a2, _TIF_WORK_MASK # (ignoring syscall_trace)
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bnez t0, work_pending
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j restore_all
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#ifdef CONFIG_PREEMPTION
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resume_kernel:
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local_irq_disable
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lw t0, TI_PRE_COUNT($28)
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bnez t0, restore_all
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LONG_L t0, TI_FLAGS($28)
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andi t1, t0, _TIF_NEED_RESCHED
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beqz t1, restore_all
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LONG_L t0, PT_STATUS(sp) # Interrupts off?
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andi t0, 1
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beqz t0, restore_all
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PTR_LA ra, restore_all
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j preempt_schedule_irq
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#endif
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FEXPORT(ret_from_kernel_thread)
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jal schedule_tail # a0 = struct task_struct *prev
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move a0, s1
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jal s0
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j syscall_exit
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FEXPORT(ret_from_fork)
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jal schedule_tail # a0 = struct task_struct *prev
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FEXPORT(syscall_exit)
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#ifdef CONFIG_DEBUG_RSEQ
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move a0, sp
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jal rseq_syscall
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#endif
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local_irq_disable # make sure need_resched and
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# signals dont change between
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# sampling and return
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LONG_L a2, TI_FLAGS($28) # current->work
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li t0, _TIF_ALLWORK_MASK
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and t0, a2, t0
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bnez t0, syscall_exit_work
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restore_all: # restore full frame
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.set noat
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RESTORE_TEMP
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RESTORE_AT
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RESTORE_STATIC
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restore_partial: # restore partial frame
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#ifdef CONFIG_TRACE_IRQFLAGS
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SAVE_STATIC
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SAVE_AT
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SAVE_TEMP
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LONG_L v0, PT_STATUS(sp)
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#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
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and v0, ST0_IEP
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#else
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and v0, ST0_IE
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#endif
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beqz v0, 1f
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jal trace_hardirqs_on
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b 2f
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1: jal trace_hardirqs_off
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2:
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RESTORE_TEMP
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RESTORE_AT
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RESTORE_STATIC
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#endif
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RESTORE_SOME
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RESTORE_SP_AND_RET
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.set at
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work_pending:
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andi t0, a2, _TIF_NEED_RESCHED # a2 is preloaded with TI_FLAGS
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beqz t0, work_notifysig
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work_resched:
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TRACE_IRQS_OFF
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jal schedule
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local_irq_disable # make sure need_resched and
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# signals dont change between
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# sampling and return
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LONG_L a2, TI_FLAGS($28)
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andi t0, a2, _TIF_WORK_MASK # is there any work to be done
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# other than syscall tracing?
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beqz t0, restore_all
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andi t0, a2, _TIF_NEED_RESCHED
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bnez t0, work_resched
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work_notifysig: # deal with pending signals and
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# notify-resume requests
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move a0, sp
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li a1, 0
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jal do_notify_resume # a2 already loaded
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j resume_userspace_check
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FEXPORT(syscall_exit_partial)
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#ifdef CONFIG_DEBUG_RSEQ
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move a0, sp
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jal rseq_syscall
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#endif
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local_irq_disable # make sure need_resched doesn't
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# change between and return
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LONG_L a2, TI_FLAGS($28) # current->work
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li t0, _TIF_ALLWORK_MASK
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and t0, a2
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beqz t0, restore_partial
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SAVE_STATIC
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syscall_exit_work:
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LONG_L t0, PT_STATUS(sp) # returning to kernel mode?
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andi t0, t0, KU_USER
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beqz t0, resume_kernel
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li t0, _TIF_WORK_SYSCALL_EXIT
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and t0, a2 # a2 is preloaded with TI_FLAGS
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beqz t0, work_pending # trace bit set?
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local_irq_enable # could let syscall_trace_leave()
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# call schedule() instead
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TRACE_IRQS_ON
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move a0, sp
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jal syscall_trace_leave
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b resume_userspace
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#if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR5) || \
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defined(CONFIG_CPU_MIPSR6) || defined(CONFIG_MIPS_MT)
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/*
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* MIPS32R2 Instruction Hazard Barrier - must be called
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*
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* For C code use the inline version named instruction_hazard().
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*/
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LEAF(mips_ihb)
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.set MIPS_ISA_LEVEL_RAW
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jr.hb ra
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nop
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END(mips_ihb)
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#endif /* CONFIG_CPU_MIPSR2 - CONFIG_CPU_MIPSR6 or CONFIG_MIPS_MT */
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