kernel_optimize_test/drivers/clk
Dmitry Osipenko d1eaf4cb44 clk: tegra: Ensure that PLLU configuration is applied properly
[ Upstream commit a7196048cd5168096c2c4f44a3939d7a6dcd06b9 ]

The PLLU (USB) consists of the PLL configuration itself and configuration
of the PLLU outputs. The PLLU programming is inconsistent on T30 vs T114,
where T114 immediately bails out if PLLU is enabled and T30 re-enables
a potentially already enabled PLL (left after bootloader) and then fully
reprograms it, which could be unsafe to do. The correct way should be to
skip enabling of the PLL if it's already enabled and then apply
configuration to the outputs. This patch doesn't fix any known problems,
it's a minor improvement.

Acked-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
2021-07-19 09:44:43 +02:00
..
actions clk: actions: Fix AHPPREDIV-H-AHB clock chain on Owl S500 SoC 2021-07-14 16:56:31 +02:00
analogbits
at91 clk: at91: sam9x60: remove atmel,osc-bypass support 2020-12-30 11:54:01 +01:00
axis
axs10x
baikal-t1
bcm clk: bcm: dvp: Add MODULE_DEVICE_TABLE() 2020-12-30 11:54:00 +01:00
berlin
davinci
h8300
hisilicon
imgtec
imx clk: imx8mq: remove SYS PLL 1/2 clock gates 2021-07-14 16:56:20 +02:00
ingenic clk: ingenic: Fix divider calculation with div tables 2020-12-30 11:54:25 +01:00
keystone
loongson1
mediatek
meson clk: meson: g12a: fix gp0 and hifi ranges 2021-07-14 16:56:16 +02:00
microchip
mmp clk: mmp2: fix build without CONFIG_PM 2021-02-03 23:28:44 +01:00
mvebu clk: mvebu: armada-37xx-periph: Fix workaround for switching from L1 to L0 2021-05-14 09:50:17 +02:00
mxs
nxp
pistachio
pxa
qcom clk: qcom: clk-alpha-pll: fix CAL_L write in alpha_pll_fabia_prepare 2021-07-14 16:56:31 +02:00
renesas clk: renesas: r8a77995: Add ZA2 clock 2021-07-19 09:44:42 +02:00
rockchip
samsung clk: exynos7: Mark aclk_fsys1_200 as critical 2021-05-19 10:13:19 +02:00
sifive
sirf
socfpga clk: agilex/stratix10: fix bypass representation 2021-07-14 16:55:44 +02:00
spear
sprd
st
sunxi
sunxi-ng clk: sunxi-ng: h6: Fix clock divider range on some clocks 2021-03-04 11:37:58 +01:00
tegra clk: tegra: Ensure that PLLU configuration is applied properly 2021-07-19 09:44:43 +02:00
ti clk: ti: Fix memleak in ti_fapll_synth_setup 2020-12-30 11:53:58 +01:00
uniphier clk: uniphier: Fix potential infinite loop 2021-05-14 09:50:26 +02:00
ux500
versatile
x86
zte
zynq
zynqmp clk: zynqmp: pll: add set_pll_mode to check condition in zynqmp_pll_enable 2021-05-14 09:50:26 +02:00
clk-asm9260.c
clk-aspeed.c
clk-aspeed.h
clk-ast2600.c media: aspeed: fix clock handling logic 2021-05-14 09:50:23 +02:00
clk-axi-clkgen.c
clk-axm5516.c
clk-bd718x7.c
clk-bm1880.c
clk-bulk.c
clk-cdce706.c
clk-cdce925.c
clk-clps711x.c
clk-composite.c
clk-conf.c
clk-cs2000-cp.c
clk-devres.c
clk-divider.c clk: divider: fix initialization with parent_hw 2021-03-04 11:38:06 +01:00
clk-efm32gg.c
clk-fixed-factor.c
clk-fixed-mmio.c
clk-fixed-rate.c
clk-fractional-divider.c
clk-fsl-sai.c clk: fsl-sai: fix memory leak 2020-12-30 11:53:42 +01:00
clk-gate.c
clk-gemini.c
clk-gpio.c
clk-hi655x.c
clk-highbank.c
clk-hsdk-pll.c
clk-lochnagar.c
clk-max9485.c
clk-max77686.c
clk-milbeaut.c
clk-moxart.c
clk-multiplier.c
clk-mux.c
clk-nomadik.c
clk-npcm7xx.c
clk-nspire.c
clk-oxnas.c
clk-palmas.c
clk-plldig.c
clk-pwm.c
clk-qoriq.c
clk-rk808.c
clk-s2mps11.c clk: s2mps11: Fix a resource leak in error handling paths in the probe function 2020-12-30 11:54:01 +01:00
clk-scmi.c
clk-scpi.c
clk-si514.c
clk-si544.c
clk-si570.c
clk-si5341.c clk: si5341: Update initialization magic 2021-07-14 16:56:31 +02:00
clk-si5351.c
clk-si5351.h
clk-sparx5.c
clk-stm32f4.c
clk-stm32h7.c
clk-stm32mp1.c
clk-tango4.c
clk-twl6040.c
clk-u300.c
clk-versaclock5.c clk: vc5: fix output disabling when enabling a FOD 2021-07-14 16:56:19 +02:00
clk-vt8500.c
clk-wm831x.c
clk-xgene.c
clk.c clk: fix invalid usage of list cursor in unregister 2021-04-14 08:42:10 +02:00
clk.h
clkdev.c
Kconfig
Makefile