kernel_optimize_test/include/dt-bindings
Lucas Stach 581098969c clk: imx8mq: remove SYS PLL 1/2 clock gates
[ Upstream commit c586f53ae159c6c1390f093a1ec94baef2df9f3a ]

Remove the PLL clock gates as the allowing to gate the sys1_pll_266m breaks
the uSDHC module which is sporadically unable to enumerate devices after
this change. Also it makes AMP clock management harder with no obvious
benefit to Linux, so just revert the change.

Link: https://lore.kernel.org/r/20210528180135.1640876-1-l.stach@pengutronix.de
Fixes: b04383b6a5 ("clk: imx8mq: Define gates for pll1/2 fixed dividers")
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Abel Vesa <abel.vesa@nxp.com>
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
2021-07-14 16:56:20 +02:00
..
arm
bus
clk
clock clk: imx8mq: remove SYS PLL 1/2 clock gates 2021-07-14 16:56:20 +02:00
display
dma
firmware/imx
gce
gpio
i2c
iio
input
interconnect dt-bindings: interconnect: Add EPSS L3 DT binding on SM8250 2020-09-08 16:29:01 +03:00
interrupt-controller
leds
mailbox
media
memory dt-bindings: iommu: Add binding for MediaTek MT8167 IOMMU 2020-09-18 10:28:48 +02:00
mfd
mips
mux dt-bindings: ti-serdes-mux: Add defines for J7200 SoC 2020-09-30 07:34:02 -05:00
net
phy dt-bindings: phy: Add PHY_TYPE_QSGMII definition 2020-09-18 10:47:19 +05:30
pinctrl ARM: SoC fixes 2020-10-24 10:26:06 -07:00
pmu
power ARM: SoC-related driver updates 2020-10-24 10:39:22 -07:00
pwm
regulator regulator: mt6360: Add support for MT6360 regulator 2020-08-26 13:41:10 +01:00
reset ARM: Devicetree updates 2020-10-24 10:44:18 -07:00
reset-controller
soc MIPS: BMIPS: add BCM6318 power domain definitions 2020-08-17 09:14:04 -07:00
sound ASoC: dt-bindings: lpass: Fix and common up lpass dai ids 2021-02-03 23:28:46 +01:00
spmi
thermal
usb