Hyok S. Choi f12d0d7c77 [ARM] nommu: manage the CP15 things ... All the current CP15 access codes in ARM arch can be categorized and conditioned by the defines as follows: Related operation Safe condition a. any CP15 access !CPU_CP15 b. alignment trap CPU_CP15_MMU c. D-cache(C-bit) CPU_CP15 d. I-cache CPU_CP15 && !( CPU_ARM610 || CPU_ARM710 || CPU_ARM720 || CPU_ARM740 || CPU_XSCALE || CPU_XSC3 ) e. alternate vector CPU_CP15 && !CPU_ARM740 f. TTB CPU_CP15_MMU g. Domain CPU_CP15_MMU h. FSR/FAR CPU_CP15_MMU For example, alternate vector is supported if and only if "CPU_CP15 && !CPU_ARM740" is satisfied. Signed-off-by: Hyok S. Choi <hyok.choi@samsung.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>		2006-09-27 17:34:30 +01:00
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bootp	kbuild: change kbuild to not rely on incorrect GNU make behavior	2006-03-06 00:09:51 +01:00
compressed	[ARM] nommu: manage the CP15 things	2006-09-27 17:34:30 +01:00
install.sh
Makefile	kbuild: change kbuild to not rely on incorrect GNU make behavior	2006-03-06 00:09:51 +01:00