forked from luck/tmp_suning_uos_patched
4a47295144
Fractional MPLLs are a superset of the existing AmLogic MPLLs. They add in a couple of new bitfields for further dividing the clock rate to achieve rates with fractional hertz. Tested-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
206 lines
5.1 KiB
C
206 lines
5.1 KiB
C
/*
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* Copyright (c) 2015 Endless Mobile, Inc.
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* Author: Carlo Caione <carlo@endlessm.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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/*
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* In the most basic form, a Meson PLL is composed as follows:
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*
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* PLL
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* +------------------------------+
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* | |
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* in -----[ /N ]---[ *M ]---[ >>OD ]----->> out
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* | ^ ^ |
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* +------------------------------+
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* | |
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* FREF VCO
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*
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* out = (in * M / N) >> OD
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*/
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#include <linux/clk-provider.h>
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/of_address.h>
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#include <linux/slab.h>
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#include <linux/string.h>
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#include "clkc.h"
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#define MESON_PLL_RESET BIT(29)
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#define MESON_PLL_LOCK BIT(31)
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#define to_meson_clk_pll(_hw) container_of(_hw, struct meson_clk_pll, hw)
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static unsigned long meson_clk_pll_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct meson_clk_pll *pll = to_meson_clk_pll(hw);
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struct parm *p;
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unsigned long parent_rate_mhz = parent_rate / 1000000;
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unsigned long rate_mhz;
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u16 n, m, frac = 0, od, od2 = 0;
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u32 reg;
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p = &pll->n;
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reg = readl(pll->base + p->reg_off);
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n = PARM_GET(p->width, p->shift, reg);
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p = &pll->m;
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reg = readl(pll->base + p->reg_off);
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m = PARM_GET(p->width, p->shift, reg);
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p = &pll->od;
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reg = readl(pll->base + p->reg_off);
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od = PARM_GET(p->width, p->shift, reg);
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p = &pll->od2;
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if (p->width) {
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reg = readl(pll->base + p->reg_off);
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od2 = PARM_GET(p->width, p->shift, reg);
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}
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p = &pll->frac;
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if (p->width) {
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reg = readl(pll->base + p->reg_off);
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frac = PARM_GET(p->width, p->shift, reg);
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rate_mhz = (parent_rate_mhz * m + \
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(parent_rate_mhz * frac >> 12)) * 2 / n;
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rate_mhz = rate_mhz >> od >> od2;
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} else
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rate_mhz = (parent_rate_mhz * m / n) >> od >> od2;
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return rate_mhz * 1000000;
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}
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static long meson_clk_pll_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *parent_rate)
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{
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struct meson_clk_pll *pll = to_meson_clk_pll(hw);
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const struct pll_rate_table *rate_table = pll->rate_table;
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int i;
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for (i = 0; i < pll->rate_count; i++) {
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if (rate <= rate_table[i].rate)
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return rate_table[i].rate;
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}
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/* else return the smallest value */
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return rate_table[0].rate;
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}
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static const struct pll_rate_table *meson_clk_get_pll_settings(struct meson_clk_pll *pll,
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unsigned long rate)
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{
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const struct pll_rate_table *rate_table = pll->rate_table;
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int i;
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for (i = 0; i < pll->rate_count; i++) {
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if (rate == rate_table[i].rate)
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return &rate_table[i];
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}
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return NULL;
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}
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static int meson_clk_pll_wait_lock(struct meson_clk_pll *pll,
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struct parm *p_n)
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{
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int delay = 24000000;
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u32 reg;
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while (delay > 0) {
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reg = readl(pll->base + p_n->reg_off);
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if (reg & MESON_PLL_LOCK)
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return 0;
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delay--;
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}
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return -ETIMEDOUT;
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}
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static int meson_clk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct meson_clk_pll *pll = to_meson_clk_pll(hw);
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struct parm *p;
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const struct pll_rate_table *rate_set;
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unsigned long old_rate;
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int ret = 0;
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u32 reg;
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if (parent_rate == 0 || rate == 0)
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return -EINVAL;
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old_rate = rate;
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rate_set = meson_clk_get_pll_settings(pll, rate);
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if (!rate_set)
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return -EINVAL;
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/* PLL reset */
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p = &pll->n;
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reg = readl(pll->base + p->reg_off);
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writel(reg | MESON_PLL_RESET, pll->base + p->reg_off);
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reg = PARM_SET(p->width, p->shift, reg, rate_set->n);
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writel(reg, pll->base + p->reg_off);
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p = &pll->m;
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reg = readl(pll->base + p->reg_off);
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reg = PARM_SET(p->width, p->shift, reg, rate_set->m);
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writel(reg, pll->base + p->reg_off);
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p = &pll->od;
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reg = readl(pll->base + p->reg_off);
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reg = PARM_SET(p->width, p->shift, reg, rate_set->od);
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writel(reg, pll->base + p->reg_off);
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p = &pll->od2;
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if (p->width) {
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reg = readl(pll->base + p->reg_off);
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reg = PARM_SET(p->width, p->shift, reg, rate_set->od2);
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writel(reg, pll->base + p->reg_off);
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}
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p = &pll->frac;
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if (p->width) {
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reg = readl(pll->base + p->reg_off);
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reg = PARM_SET(p->width, p->shift, reg, rate_set->frac);
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writel(reg, pll->base + p->reg_off);
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}
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p = &pll->n;
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ret = meson_clk_pll_wait_lock(pll, p);
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if (ret) {
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pr_warn("%s: pll did not lock, trying to restore old rate %lu\n",
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__func__, old_rate);
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meson_clk_pll_set_rate(hw, old_rate, parent_rate);
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}
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return ret;
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}
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const struct clk_ops meson_clk_pll_ops = {
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.recalc_rate = meson_clk_pll_recalc_rate,
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.round_rate = meson_clk_pll_round_rate,
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.set_rate = meson_clk_pll_set_rate,
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};
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const struct clk_ops meson_clk_pll_ro_ops = {
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.recalc_rate = meson_clk_pll_recalc_rate,
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};
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