forked from luck/tmp_suning_uos_patched
c37d4a0085
Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com> Signed-off-by: David S. Miller <davem@davemloft.net>
135 lines
3.4 KiB
C
135 lines
3.4 KiB
C
/*
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* drivers/tdm/line_ctrl/slic_ds26522.h
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*
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* Copyright 2016 Freescale Semiconductor, Inc.
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*
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* Author: Zhao Qiang <B45475@freescale.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#define DS26522_RF_ADDR_START 0x00
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#define DS26522_RF_ADDR_END 0xef
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#define DS26522_GLB_ADDR_START 0xf0
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#define DS26522_GLB_ADDR_END 0xff
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#define DS26522_TF_ADDR_START 0x100
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#define DS26522_TF_ADDR_END 0x1ef
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#define DS26522_LIU_ADDR_START 0x1000
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#define DS26522_LIU_ADDR_END 0x101f
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#define DS26522_TEST_ADDR_START 0x1008
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#define DS26522_TEST_ADDR_END 0x101f
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#define DS26522_BERT_ADDR_START 0x1100
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#define DS26522_BERT_ADDR_END 0x110f
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#define DS26522_RMMR_ADDR 0x80
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#define DS26522_RCR1_ADDR 0x81
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#define DS26522_RCR3_ADDR 0x83
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#define DS26522_RIOCR_ADDR 0x84
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#define DS26522_GTCR1_ADDR 0xf0
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#define DS26522_GFCR_ADDR 0xf1
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#define DS26522_GTCR2_ADDR 0xf2
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#define DS26522_GTCCR_ADDR 0xf3
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#define DS26522_GLSRR_ADDR 0xf5
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#define DS26522_GFSRR_ADDR 0xf6
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#define DS26522_IDR_ADDR 0xf8
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#define DS26522_E1TAF_ADDR 0x164
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#define DS26522_E1TNAF_ADDR 0x165
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#define DS26522_TMMR_ADDR 0x180
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#define DS26522_TCR1_ADDR 0x181
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#define DS26522_TIOCR_ADDR 0x184
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#define DS26522_LTRCR_ADDR 0x1000
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#define DS26522_LTITSR_ADDR 0x1001
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#define DS26522_LMCR_ADDR 0x1002
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#define DS26522_LRISMR_ADDR 0x1007
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#define MAX_NUM_OF_CHANNELS 8
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#define PQ_MDS_8E1T1_BRD_REV 0x00
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#define PQ_MDS_8E1T1_PLD_REV 0x00
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#define DS26522_GTCCR_BPREFSEL_REFCLKIN 0xa0
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#define DS26522_GTCCR_BFREQSEL_1544KHZ 0x08
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#define DS26522_GTCCR_FREQSEL_1544KHZ 0x04
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#define DS26522_GTCCR_BFREQSEL_2048KHZ 0x00
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#define DS26522_GTCCR_FREQSEL_2048KHZ 0x00
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#define DS26522_GFCR_BPCLK_2048KHZ 0x00
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#define DS26522_GTCR2_TSSYNCOUT 0x02
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#define DS26522_GTCR1 0x00
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#define DS26522_GFSRR_RESET 0x01
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#define DS26522_GFSRR_NORMAL 0x00
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#define DS26522_GLSRR_RESET 0x01
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#define DS26522_GLSRR_NORMAL 0x00
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#define DS26522_RMMR_SFTRST 0x02
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#define DS26522_RMMR_FRM_EN 0x80
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#define DS26522_RMMR_INIT_DONE 0x40
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#define DS26522_RMMR_T1 0x00
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#define DS26522_RMMR_E1 0x01
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#define DS26522_E1TAF_DEFAULT 0x1b
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#define DS26522_E1TNAF_DEFAULT 0x40
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#define DS26522_TMMR_SFTRST 0x02
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#define DS26522_TMMR_FRM_EN 0x80
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#define DS26522_TMMR_INIT_DONE 0x40
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#define DS26522_TMMR_T1 0x00
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#define DS26522_TMMR_E1 0x01
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#define DS26522_RCR1_T1_SYNCT 0x80
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#define DS26522_RCR1_T1_RB8ZS 0x40
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#define DS26522_RCR1_T1_SYNCC 0x08
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#define DS26522_RCR1_E1_HDB3 0x40
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#define DS26522_RCR1_E1_CCS 0x20
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#define DS26522_RIOCR_1544KHZ 0x00
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#define DS26522_RIOCR_2048KHZ 0x10
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#define DS26522_RIOCR_RSIO_OUT 0x00
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#define DS26522_RCR3_FLB 0x01
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#define DS26522_TIOCR_1544KHZ 0x00
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#define DS26522_TIOCR_2048KHZ 0x10
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#define DS26522_TIOCR_TSIO_OUT 0x04
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#define DS26522_TCR1_TB8ZS 0x04
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#define DS26522_LTRCR_T1 0x02
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#define DS26522_LTRCR_E1 0x00
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#define DS26522_LTITSR_TLIS_75OHM 0x00
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#define DS26522_LTITSR_LBOS_75OHM 0x00
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#define DS26522_LTITSR_TLIS_100OHM 0x10
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#define DS26522_LTITSR_TLIS_0DB_CSU 0x00
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#define DS26522_LRISMR_75OHM 0x00
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#define DS26522_LRISMR_100OHM 0x10
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#define DS26522_LRISMR_MAX 0x03
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#define DS26522_LMCR_TE 0x01
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enum line_rate {
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LINE_RATE_T1, /* T1 line rate (1.544 Mbps) */
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LINE_RATE_E1 /* E1 line rate (2.048 Mbps) */
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};
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enum tdm_trans_mode {
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NORMAL = 0,
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FRAMER_LB
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};
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enum card_support_type {
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LM_CARD = 0,
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DS26522_CARD,
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NO_CARD
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};
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