forked from luck/tmp_suning_uos_patched
04cc058f0c
The next generation Intel GPIO hardware supports additional 1k pull-down per-pad. Add support for this to the Intel core pinctrl driver. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
136 lines
4.0 KiB
C
136 lines
4.0 KiB
C
/*
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* Core pinctrl/GPIO driver for Intel GPIO controllers
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*
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* Copyright (C) 2015, Intel Corporation
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* Authors: Mathias Nyman <mathias.nyman@linux.intel.com>
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* Mika Westerberg <mika.westerberg@linux.intel.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef PINCTRL_INTEL_H
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#define PINCTRL_INTEL_H
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struct pinctrl_pin_desc;
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struct platform_device;
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struct device;
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/**
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* struct intel_pingroup - Description about group of pins
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* @name: Name of the groups
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* @pins: All pins in this group
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* @npins: Number of pins in this groups
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* @mode: Native mode in which the group is muxed out @pins
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*/
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struct intel_pingroup {
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const char *name;
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const unsigned *pins;
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size_t npins;
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unsigned short mode;
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};
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/**
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* struct intel_function - Description about a function
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* @name: Name of the function
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* @groups: An array of groups for this function
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* @ngroups: Number of groups in @groups
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*/
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struct intel_function {
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const char *name;
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const char * const *groups;
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size_t ngroups;
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};
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/**
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* struct intel_community - Intel pin community description
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* @barno: MMIO BAR number where registers for this community reside
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* @padown_offset: Register offset of PAD_OWN register from @regs. If %0
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* then there is no support for owner.
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* @padcfglock_offset: Register offset of PADCFGLOCK from @regs. If %0 then
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* locking is not supported.
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* @hostown_offset: Register offset of HOSTSW_OWN from @regs. If %0 then it
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* is assumed that the host owns the pin (rather than
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* ACPI).
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* @ie_offset: Register offset of GPI_IE from @regs.
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* @pin_base: Starting pin of pins in this community
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* @gpp_size: Maximum number of pads in each group, such as PADCFGLOCK,
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* HOSTSW_OWN, GPI_IS, GPI_IE, etc.
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* @npins: Number of pins in this community
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* @features: Additional features supported by the hardware
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* @regs: Community specific common registers (reserved for core driver)
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* @pad_regs: Community specific pad registers (reserved for core driver)
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* @ngpps: Number of groups (hw groups) in this community (reserved for
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* core driver)
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*/
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struct intel_community {
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unsigned barno;
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unsigned padown_offset;
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unsigned padcfglock_offset;
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unsigned hostown_offset;
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unsigned ie_offset;
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unsigned pin_base;
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unsigned gpp_size;
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size_t npins;
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unsigned features;
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void __iomem *regs;
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void __iomem *pad_regs;
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size_t ngpps;
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};
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/* Additional features supported by the hardware */
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#define PINCTRL_FEATURE_DEBOUNCE BIT(0)
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#define PINCTRL_FEATURE_1K_PD BIT(1)
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#define PIN_GROUP(n, p, m) \
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{ \
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.name = (n), \
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.pins = (p), \
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.npins = ARRAY_SIZE((p)), \
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.mode = (m), \
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}
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#define FUNCTION(n, g) \
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{ \
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.name = (n), \
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.groups = (g), \
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.ngroups = ARRAY_SIZE((g)), \
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}
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/**
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* struct intel_pinctrl_soc_data - Intel pin controller per-SoC configuration
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* @uid: ACPI _UID for the probe driver use if needed
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* @pins: Array if pins this pinctrl controls
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* @npins: Number of pins in the array
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* @groups: Array of pin groups
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* @ngroups: Number of groups in the array
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* @functions: Array of functions
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* @nfunctions: Number of functions in the array
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* @communities: Array of communities this pinctrl handles
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* @ncommunities: Number of communities in the array
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*
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* The @communities is used as a template by the core driver. It will make
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* copy of all communities and fill in rest of the information.
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*/
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struct intel_pinctrl_soc_data {
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const char *uid;
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const struct pinctrl_pin_desc *pins;
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size_t npins;
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const struct intel_pingroup *groups;
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size_t ngroups;
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const struct intel_function *functions;
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size_t nfunctions;
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const struct intel_community *communities;
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size_t ncommunities;
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};
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int intel_pinctrl_probe(struct platform_device *pdev,
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const struct intel_pinctrl_soc_data *soc_data);
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#ifdef CONFIG_PM_SLEEP
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int intel_pinctrl_suspend(struct device *dev);
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int intel_pinctrl_resume(struct device *dev);
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#endif
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#endif /* PINCTRL_INTEL_H */
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