forked from luck/tmp_suning_uos_patched
04b73b1571
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
294 lines
8.4 KiB
C
294 lines
8.4 KiB
C
/*
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*
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* Copyright (C) 2010 Eric Bénard <eric@eukrea.com>
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*
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* based on board-mx51_babbage.c which is
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* Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
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* Copyright (C) 2009-2010 Amit Kucheria <amit.kucheria@canonical.com>
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*
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* The code contained herein is licensed under the GNU General Public
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* License. You may obtain a copy of the GNU General Public License
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* Version 2 or later at the following locations:
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*
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*/
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#include <linux/init.h>
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#include <linux/platform_device.h>
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#include <linux/serial_8250.h>
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#include <linux/i2c.h>
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#include <linux/gpio.h>
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/fsl_devices.h>
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#include <mach/eukrea-baseboards.h>
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#include <mach/common.h>
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#include <mach/hardware.h>
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#include <mach/iomux-mx51.h>
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#include <mach/mxc_ehci.h>
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#include <asm/irq.h>
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#include <asm/setup.h>
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#include <asm/mach-types.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/time.h>
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#include "devices-imx51.h"
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#include "devices.h"
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#define CPUIMX51_USBH1_STP (0*32 + 27)
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#define CPUIMX51_QUARTA_GPIO (2*32 + 28)
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#define CPUIMX51_QUARTB_GPIO (2*32 + 25)
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#define CPUIMX51_QUARTC_GPIO (2*32 + 26)
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#define CPUIMX51_QUARTD_GPIO (2*32 + 27)
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#define CPUIMX51_QUARTA_IRQ (MXC_INTERNAL_IRQS + CPUIMX51_QUARTA_GPIO)
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#define CPUIMX51_QUARTB_IRQ (MXC_INTERNAL_IRQS + CPUIMX51_QUARTB_GPIO)
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#define CPUIMX51_QUARTC_IRQ (MXC_INTERNAL_IRQS + CPUIMX51_QUARTC_GPIO)
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#define CPUIMX51_QUARTD_IRQ (MXC_INTERNAL_IRQS + CPUIMX51_QUARTD_GPIO)
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#define CPUIMX51_QUART_XTAL 14745600
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#define CPUIMX51_QUART_REGSHIFT 17
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/* USB_CTRL_1 */
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#define MX51_USB_CTRL_1_OFFSET 0x10
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#define MX51_USB_CTRL_UH1_EXT_CLK_EN (1 << 25)
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#define MX51_USB_PLLDIV_12_MHZ 0x00
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#define MX51_USB_PLL_DIV_19_2_MHZ 0x01
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#define MX51_USB_PLL_DIV_24_MHZ 0x02
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#if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE)
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static struct plat_serial8250_port serial_platform_data[] = {
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{
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.mapbase = (unsigned long)(MX51_CS1_BASE_ADDR + 0x400000),
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.irq = CPUIMX51_QUARTA_IRQ,
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.irqflags = IRQF_TRIGGER_HIGH,
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.uartclk = CPUIMX51_QUART_XTAL,
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.regshift = CPUIMX51_QUART_REGSHIFT,
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.iotype = UPIO_MEM,
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.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP,
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}, {
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.mapbase = (unsigned long)(MX51_CS1_BASE_ADDR + 0x800000),
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.irq = CPUIMX51_QUARTB_IRQ,
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.irqflags = IRQF_TRIGGER_HIGH,
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.uartclk = CPUIMX51_QUART_XTAL,
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.regshift = CPUIMX51_QUART_REGSHIFT,
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.iotype = UPIO_MEM,
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.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP,
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}, {
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.mapbase = (unsigned long)(MX51_CS1_BASE_ADDR + 0x1000000),
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.irq = CPUIMX51_QUARTC_IRQ,
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.irqflags = IRQF_TRIGGER_HIGH,
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.uartclk = CPUIMX51_QUART_XTAL,
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.regshift = CPUIMX51_QUART_REGSHIFT,
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.iotype = UPIO_MEM,
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.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP,
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}, {
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.mapbase = (unsigned long)(MX51_CS1_BASE_ADDR + 0x2000000),
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.irq = CPUIMX51_QUARTD_IRQ,
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.irqflags = IRQF_TRIGGER_HIGH,
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.uartclk = CPUIMX51_QUART_XTAL,
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.regshift = CPUIMX51_QUART_REGSHIFT,
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.iotype = UPIO_MEM,
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.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP,
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}, {
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}
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};
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static struct platform_device serial_device = {
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.name = "serial8250",
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.id = 0,
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.dev = {
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.platform_data = serial_platform_data,
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},
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};
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#endif
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static struct platform_device *devices[] __initdata = {
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&mxc_fec_device,
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#if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE)
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&serial_device,
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#endif
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};
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static struct pad_desc eukrea_cpuimx51_pads[] = {
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/* UART1 */
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MX51_PAD_UART1_RXD__UART1_RXD,
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MX51_PAD_UART1_TXD__UART1_TXD,
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MX51_PAD_UART1_RTS__UART1_RTS,
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MX51_PAD_UART1_CTS__UART1_CTS,
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/* I2C2 */
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MX51_PAD_GPIO_1_2__I2C2_SCL,
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MX51_PAD_GPIO_1_3__I2C2_SDA,
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MX51_PAD_NANDF_D10__GPIO_3_30,
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/* QUART IRQ */
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MX51_PAD_NANDF_D15__GPIO_3_25,
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MX51_PAD_NANDF_D14__GPIO_3_26,
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MX51_PAD_NANDF_D13__GPIO_3_27,
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MX51_PAD_NANDF_D12__GPIO_3_28,
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/* USB HOST1 */
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MX51_PAD_USBH1_CLK__USBH1_CLK,
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MX51_PAD_USBH1_DIR__USBH1_DIR,
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MX51_PAD_USBH1_NXT__USBH1_NXT,
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MX51_PAD_USBH1_DATA0__USBH1_DATA0,
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MX51_PAD_USBH1_DATA1__USBH1_DATA1,
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MX51_PAD_USBH1_DATA2__USBH1_DATA2,
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MX51_PAD_USBH1_DATA3__USBH1_DATA3,
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MX51_PAD_USBH1_DATA4__USBH1_DATA4,
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MX51_PAD_USBH1_DATA5__USBH1_DATA5,
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MX51_PAD_USBH1_DATA6__USBH1_DATA6,
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MX51_PAD_USBH1_DATA7__USBH1_DATA7,
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MX51_PAD_USBH1_STP__USBH1_STP,
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};
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static const struct imxuart_platform_data uart_pdata __initconst = {
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.flags = IMXUART_HAVE_RTSCTS,
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};
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static const
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struct imxi2c_platform_data eukrea_cpuimx51_i2c_data __initconst = {
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.bitrate = 100000,
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};
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static struct i2c_board_info eukrea_cpuimx51_i2c_devices[] = {
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{
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I2C_BOARD_INFO("pcf8563", 0x51),
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},
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};
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/* This function is board specific as the bit mask for the plldiv will also
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be different for other Freescale SoCs, thus a common bitmask is not
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possible and cannot get place in /plat-mxc/ehci.c.*/
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static int initialize_otg_port(struct platform_device *pdev)
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{
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u32 v;
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void __iomem *usb_base;
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void __iomem *usbother_base;
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usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
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usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
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/* Set the PHY clock to 19.2MHz */
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v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
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v &= ~MX5_USB_UTMI_PHYCTRL1_PLLDIV_MASK;
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v |= MX51_USB_PLL_DIV_19_2_MHZ;
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__raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
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iounmap(usb_base);
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return 0;
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}
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static int initialize_usbh1_port(struct platform_device *pdev)
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{
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u32 v;
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void __iomem *usb_base;
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void __iomem *usbother_base;
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usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
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usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
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/* The clock for the USBH1 ULPI port will come externally from the PHY. */
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v = __raw_readl(usbother_base + MX51_USB_CTRL_1_OFFSET);
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__raw_writel(v | MX51_USB_CTRL_UH1_EXT_CLK_EN, usbother_base + MX51_USB_CTRL_1_OFFSET);
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iounmap(usb_base);
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return 0;
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}
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static struct mxc_usbh_platform_data dr_utmi_config = {
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.init = initialize_otg_port,
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.portsc = MXC_EHCI_UTMI_16BIT,
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.flags = MXC_EHCI_INTERNAL_PHY,
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};
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static struct fsl_usb2_platform_data usb_pdata = {
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.operating_mode = FSL_USB2_DR_DEVICE,
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.phy_mode = FSL_USB2_PHY_UTMI_WIDE,
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};
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static struct mxc_usbh_platform_data usbh1_config = {
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.init = initialize_usbh1_port,
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.portsc = MXC_EHCI_MODE_ULPI,
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.flags = (MXC_EHCI_POWER_PINS_ENABLED | MXC_EHCI_ITC_NO_THRESHOLD),
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};
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static int otg_mode_host;
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static int __init eukrea_cpuimx51_otg_mode(char *options)
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{
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if (!strcmp(options, "host"))
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otg_mode_host = 1;
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else if (!strcmp(options, "device"))
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otg_mode_host = 0;
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else
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pr_info("otg_mode neither \"host\" nor \"device\". "
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"Defaulting to device\n");
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return 0;
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}
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__setup("otg_mode=", eukrea_cpuimx51_otg_mode);
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/*
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* Board specific initialization.
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*/
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static void __init eukrea_cpuimx51_init(void)
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{
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mxc_iomux_v3_setup_multiple_pads(eukrea_cpuimx51_pads,
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ARRAY_SIZE(eukrea_cpuimx51_pads));
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imx51_add_imx_uart(0, &uart_pdata);
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gpio_request(CPUIMX51_QUARTA_GPIO, "quarta_irq");
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gpio_direction_input(CPUIMX51_QUARTA_GPIO);
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gpio_free(CPUIMX51_QUARTA_GPIO);
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gpio_request(CPUIMX51_QUARTB_GPIO, "quartb_irq");
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gpio_direction_input(CPUIMX51_QUARTB_GPIO);
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gpio_free(CPUIMX51_QUARTB_GPIO);
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gpio_request(CPUIMX51_QUARTC_GPIO, "quartc_irq");
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gpio_direction_input(CPUIMX51_QUARTC_GPIO);
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gpio_free(CPUIMX51_QUARTC_GPIO);
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gpio_request(CPUIMX51_QUARTD_GPIO, "quartd_irq");
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gpio_direction_input(CPUIMX51_QUARTD_GPIO);
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gpio_free(CPUIMX51_QUARTD_GPIO);
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platform_add_devices(devices, ARRAY_SIZE(devices));
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imx51_add_imx_i2c(1, &eukrea_cpuimx51_i2c_data);
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i2c_register_board_info(1, eukrea_cpuimx51_i2c_devices,
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ARRAY_SIZE(eukrea_cpuimx51_i2c_devices));
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if (otg_mode_host)
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mxc_register_device(&mxc_usbdr_host_device, &dr_utmi_config);
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else {
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initialize_otg_port(NULL);
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mxc_register_device(&mxc_usbdr_udc_device, &usb_pdata);
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}
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mxc_register_device(&mxc_usbh1_device, &usbh1_config);
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#ifdef CONFIG_MACH_EUKREA_MBIMX51_BASEBOARD
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eukrea_mbimx51_baseboard_init();
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#endif
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}
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static void __init eukrea_cpuimx51_timer_init(void)
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{
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mx51_clocks_init(32768, 24000000, 22579200, 0);
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}
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static struct sys_timer mxc_timer = {
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.init = eukrea_cpuimx51_timer_init,
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};
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MACHINE_START(EUKREA_CPUIMX51, "Eukrea CPUIMX51 Module")
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/* Maintainer: Eric Bénard <eric@eukrea.com> */
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.phys_io = MX51_AIPS1_BASE_ADDR,
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.io_pg_offst = ((MX51_AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
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.boot_params = PHYS_OFFSET + 0x100,
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.map_io = mx51_map_io,
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.init_irq = mx51_init_irq,
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.init_machine = eukrea_cpuimx51_init,
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.timer = &mxc_timer,
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MACHINE_END
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