forked from luck/tmp_suning_uos_patched
842dfc11ea
Starting with version 2.24.51.20140728 MIPS binutils complain loudly
about mixing soft-float and hard-float object files, leading to this
build failure since GCC is invoked with "-msoft-float" on MIPS:
{standard input}: Warning: .gnu_attribute 4,3 requires `softfloat'
LD arch/mips/alchemy/common/built-in.o
mipsel-softfloat-linux-gnu-ld: Warning: arch/mips/alchemy/common/built-in.o
uses -msoft-float (set by arch/mips/alchemy/common/prom.o),
arch/mips/alchemy/common/sleeper.o uses -mhard-float
To fix this, we detect if GAS is new enough to support "-msoft-float" command
option, and if it does, we can let GCC pass it to GAS; but then we also need
to sprinkle the files which make use of floating point registers with the
necessary ".set hardfloat" directives.
Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com>
Cc: Linux-MIPS <linux-mips@linux-mips.org>
Cc: Matthew Fortune <Matthew.Fortune@imgtec.com>
Cc: Markos Chandras <Markos.Chandras@imgtec.com>
Cc: Maciej W. Rozycki <macro@linux-mips.org>
Patchwork: https://patchwork.linux-mips.org/patch/8355/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
93 lines
2.3 KiB
ArmAsm
93 lines
2.3 KiB
ArmAsm
/*
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* r6000_fpu.S: Save/restore floating point context for signal handlers.
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 1996 by Ralf Baechle
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*
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* Multi-arch abstraction and asm macros for easier reading:
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* Copyright (C) 1996 David S. Miller (davem@davemloft.net)
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*/
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#include <asm/asm.h>
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#include <asm/fpregdef.h>
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#include <asm/mipsregs.h>
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#include <asm/asm-offsets.h>
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#include <asm/regdef.h>
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.set noreorder
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.set mips2
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.set push
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SET_HARDFLOAT
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/* Save floating point context */
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LEAF(_save_fp_context)
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mfc0 t0,CP0_STATUS
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sll t0,t0,2
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bgez t0,1f
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nop
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cfc1 t1,fcr31
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/* Store the 16 double precision registers */
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sdc1 $f0,(SC_FPREGS+0)(a0)
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sdc1 $f2,(SC_FPREGS+16)(a0)
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sdc1 $f4,(SC_FPREGS+32)(a0)
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sdc1 $f6,(SC_FPREGS+48)(a0)
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sdc1 $f8,(SC_FPREGS+64)(a0)
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sdc1 $f10,(SC_FPREGS+80)(a0)
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sdc1 $f12,(SC_FPREGS+96)(a0)
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sdc1 $f14,(SC_FPREGS+112)(a0)
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sdc1 $f16,(SC_FPREGS+128)(a0)
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sdc1 $f18,(SC_FPREGS+144)(a0)
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sdc1 $f20,(SC_FPREGS+160)(a0)
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sdc1 $f22,(SC_FPREGS+176)(a0)
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sdc1 $f24,(SC_FPREGS+192)(a0)
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sdc1 $f26,(SC_FPREGS+208)(a0)
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sdc1 $f28,(SC_FPREGS+224)(a0)
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sdc1 $f30,(SC_FPREGS+240)(a0)
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jr ra
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sw t0,SC_FPC_CSR(a0)
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1: jr ra
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nop
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END(_save_fp_context)
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/* Restore FPU state:
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* - fp gp registers
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* - cp1 status/control register
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*
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* We base the decision which registers to restore from the signal stack
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* frame on the current content of c0_status, not on the content of the
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* stack frame which might have been changed by the user.
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*/
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LEAF(_restore_fp_context)
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mfc0 t0,CP0_STATUS
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sll t0,t0,2
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bgez t0,1f
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lw t0,SC_FPC_CSR(a0)
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/* Restore the 16 double precision registers */
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ldc1 $f0,(SC_FPREGS+0)(a0)
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ldc1 $f2,(SC_FPREGS+16)(a0)
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ldc1 $f4,(SC_FPREGS+32)(a0)
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ldc1 $f6,(SC_FPREGS+48)(a0)
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ldc1 $f8,(SC_FPREGS+64)(a0)
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ldc1 $f10,(SC_FPREGS+80)(a0)
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ldc1 $f12,(SC_FPREGS+96)(a0)
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ldc1 $f14,(SC_FPREGS+112)(a0)
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ldc1 $f16,(SC_FPREGS+128)(a0)
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ldc1 $f18,(SC_FPREGS+144)(a0)
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ldc1 $f20,(SC_FPREGS+160)(a0)
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ldc1 $f22,(SC_FPREGS+176)(a0)
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ldc1 $f24,(SC_FPREGS+192)(a0)
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ldc1 $f26,(SC_FPREGS+208)(a0)
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ldc1 $f28,(SC_FPREGS+224)(a0)
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ldc1 $f30,(SC_FPREGS+240)(a0)
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jr ra
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ctc1 t0,fcr31
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1: jr ra
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nop
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END(_restore_fp_context)
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.set pop /* SET_HARDFLOAT */
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