forked from luck/tmp_suning_uos_patched
422e23ea08
We use clock cycle counter, adjusted to HZ. This can be extended to sun4v based processors as well, as they also have a proper overflow interrupt facility for the performance counters. Signed-off-by: David S. Miller <davem@davemloft.net>
132 lines
2.4 KiB
C
132 lines
2.4 KiB
C
/**
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* @file init.c
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*
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* @remark Copyright 2002 OProfile authors
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* @remark Read the file COPYING
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*
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* @author John Levon <levon@movementarian.org>
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*/
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#include <linux/kernel.h>
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#include <linux/oprofile.h>
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#include <linux/errno.h>
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#include <linux/init.h>
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#ifdef CONFIG_SPARC64
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#include <asm/spitfire.h>
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#include <asm/cpudata.h>
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#include <asm/irq.h>
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static int nmi_enabled;
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static u64 picl_value(void)
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{
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u32 delta = local_cpu_data().clock_tick / HZ;
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return (0 - delta) & 0xffffffff;
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}
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#define PCR_PIC_PRIV 0x1 /* PIC access is privileged */
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#define PCR_STRACE 0x2 /* Trace supervisor events */
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#define PCR_UTRACE 0x4 /* Trace user events */
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static void nmi_handler(struct pt_regs *regs)
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{
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write_pcr(PCR_PIC_PRIV);
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if (nmi_enabled) {
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oprofile_add_sample(regs, 0);
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write_pic(picl_value());
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write_pcr(PCR_PIC_PRIV | PCR_STRACE | PCR_UTRACE);
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}
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}
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/* We count "clock cycle" events in the lower 32-bit PIC.
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* Then configure it such that it overflows every HZ, and thus
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* generates a level 15 interrupt at that frequency.
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*/
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static void cpu_nmi_start(void *_unused)
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{
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write_pcr(PCR_PIC_PRIV);
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write_pic(picl_value());
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/* Bit 0: PIC access is privileged
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* Bit 1: Supervisor Trace
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* Bit 2: User Trace
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*
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* And the event selection code for cpu cycles is zero.
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*/
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write_pcr(PCR_PIC_PRIV | PCR_STRACE | PCR_UTRACE);
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}
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static void cpu_nmi_stop(void *_unused)
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{
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write_pcr(PCR_PIC_PRIV);
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}
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static int nmi_start(void)
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{
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int err = register_perfctr_intr(nmi_handler);
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if (!err) {
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nmi_enabled = 1;
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wmb();
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err = on_each_cpu(cpu_nmi_start, NULL, 1);
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if (err) {
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nmi_enabled = 0;
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wmb();
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on_each_cpu(cpu_nmi_stop, NULL, 1);
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release_perfctr_intr(nmi_handler);
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}
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}
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return err;
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}
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static void nmi_stop(void)
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{
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nmi_enabled = 0;
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wmb();
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on_each_cpu(cpu_nmi_stop, NULL, 1);
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release_perfctr_intr(nmi_handler);
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synchronize_sched();
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}
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static int oprofile_nmi_init(struct oprofile_operations *ops)
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{
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if (tlb_type != cheetah && tlb_type != cheetah_plus)
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return -ENODEV;
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ops->create_files = NULL;
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ops->setup = NULL;
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ops->shutdown = NULL;
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ops->start = nmi_start;
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ops->stop = nmi_stop;
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ops->cpu_type = "timer";
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printk(KERN_INFO "oprofile: Using perfctr based NMI timer interrupt.\n");
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return 0;
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}
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#endif
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int __init oprofile_arch_init(struct oprofile_operations *ops)
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{
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int ret = -ENODEV;
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#ifdef CONFIG_SPARC64
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ret = oprofile_nmi_init(ops);
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if (!ret)
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return ret;
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#endif
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return ret;
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}
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void oprofile_arch_exit(void)
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{
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}
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