forked from luck/tmp_suning_uos_patched
6d1966dfd6
Register MIDR_EL1 is masked to get variant and revision fields, then compared against midr_range_min and midr_range_max when checking whether CPU is affected by any particular erratum. However, variant and revision fields in MIDR_EL1 are separated by 16 bits, so the min and max of midr range should be constructed accordingly, otherwise the patch will not be applied when variant field is non-0. Cc: stable@vger.kernel.org # 3.19+ Acked-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Bo Yan <byan@nvidia.com> [will: use MIDR_VARIANT_SHIFT to construct upper bound] Signed-off-by: Will Deacon <will.deacon@arm.com>
93 lines
2.5 KiB
C
93 lines
2.5 KiB
C
/*
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* Contains CPU specific errata definitions
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*
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* Copyright (C) 2014 ARM Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/types.h>
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#include <asm/cpu.h>
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#include <asm/cputype.h>
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#include <asm/cpufeature.h>
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#define MIDR_CORTEX_A53 MIDR_CPU_PART(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A53)
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#define MIDR_CORTEX_A57 MIDR_CPU_PART(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A57)
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#define CPU_MODEL_MASK (MIDR_IMPLEMENTOR_MASK | MIDR_PARTNUM_MASK | \
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MIDR_ARCHITECTURE_MASK)
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static bool __maybe_unused
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is_affected_midr_range(const struct arm64_cpu_capabilities *entry)
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{
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u32 midr = read_cpuid_id();
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if ((midr & CPU_MODEL_MASK) != entry->midr_model)
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return false;
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midr &= MIDR_REVISION_MASK | MIDR_VARIANT_MASK;
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return (midr >= entry->midr_range_min && midr <= entry->midr_range_max);
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}
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#define MIDR_RANGE(model, min, max) \
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.matches = is_affected_midr_range, \
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.midr_model = model, \
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.midr_range_min = min, \
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.midr_range_max = max
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const struct arm64_cpu_capabilities arm64_errata[] = {
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#if defined(CONFIG_ARM64_ERRATUM_826319) || \
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defined(CONFIG_ARM64_ERRATUM_827319) || \
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defined(CONFIG_ARM64_ERRATUM_824069)
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{
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/* Cortex-A53 r0p[012] */
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.desc = "ARM errata 826319, 827319, 824069",
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.capability = ARM64_WORKAROUND_CLEAN_CACHE,
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MIDR_RANGE(MIDR_CORTEX_A53, 0x00, 0x02),
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},
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#endif
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#ifdef CONFIG_ARM64_ERRATUM_819472
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{
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/* Cortex-A53 r0p[01] */
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.desc = "ARM errata 819472",
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.capability = ARM64_WORKAROUND_CLEAN_CACHE,
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MIDR_RANGE(MIDR_CORTEX_A53, 0x00, 0x01),
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},
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#endif
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#ifdef CONFIG_ARM64_ERRATUM_832075
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{
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/* Cortex-A57 r0p0 - r1p2 */
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.desc = "ARM erratum 832075",
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.capability = ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE,
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MIDR_RANGE(MIDR_CORTEX_A57, 0x00,
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(1 << MIDR_VARIANT_SHIFT) | 2),
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},
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#endif
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#ifdef CONFIG_ARM64_ERRATUM_845719
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{
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/* Cortex-A53 r0p[01234] */
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.desc = "ARM erratum 845719",
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.capability = ARM64_WORKAROUND_845719,
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MIDR_RANGE(MIDR_CORTEX_A53, 0x00, 0x04),
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},
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#endif
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{
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}
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};
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void check_local_cpu_errata(void)
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{
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check_cpu_capabilities(arm64_errata, "enabling workaround for");
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}
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