forked from luck/tmp_suning_uos_patched
b29e8b87d5
Add OF support for the CPU and MISC interrupt controllers of most supported ATH79 devices. Signed-off-by: Alban Bedel <albeu@free.fr> Cc: linux-mips@linux-mips.org Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
374 lines
8.8 KiB
C
374 lines
8.8 KiB
C
/*
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* Atheros AR71xx/AR724x/AR913x specific interrupt handling
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*
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* Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
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* Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
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* Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
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*
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* Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/irqchip.h>
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#include <linux/of_irq.h>
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#include "../../../drivers/irqchip/irqchip.h"
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#include <asm/irq_cpu.h>
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#include <asm/mipsregs.h>
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#include <asm/mach-ath79/ath79.h>
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#include <asm/mach-ath79/ar71xx_regs.h>
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#include "common.h"
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#include "machtypes.h"
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static void ath79_misc_irq_handler(unsigned int irq, struct irq_desc *desc)
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{
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void __iomem *base = ath79_reset_base;
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u32 pending;
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pending = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_STATUS) &
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__raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE);
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if (!pending) {
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spurious_interrupt();
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return;
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}
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while (pending) {
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int bit = __ffs(pending);
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generic_handle_irq(ATH79_MISC_IRQ(bit));
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pending &= ~BIT(bit);
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}
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}
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static void ar71xx_misc_irq_unmask(struct irq_data *d)
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{
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unsigned int irq = d->irq - ATH79_MISC_IRQ_BASE;
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void __iomem *base = ath79_reset_base;
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u32 t;
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t = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE);
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__raw_writel(t | (1 << irq), base + AR71XX_RESET_REG_MISC_INT_ENABLE);
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/* flush write */
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__raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE);
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}
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static void ar71xx_misc_irq_mask(struct irq_data *d)
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{
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unsigned int irq = d->irq - ATH79_MISC_IRQ_BASE;
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void __iomem *base = ath79_reset_base;
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u32 t;
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t = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE);
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__raw_writel(t & ~(1 << irq), base + AR71XX_RESET_REG_MISC_INT_ENABLE);
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/* flush write */
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__raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE);
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}
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static void ar724x_misc_irq_ack(struct irq_data *d)
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{
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unsigned int irq = d->irq - ATH79_MISC_IRQ_BASE;
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void __iomem *base = ath79_reset_base;
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u32 t;
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t = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_STATUS);
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__raw_writel(t & ~(1 << irq), base + AR71XX_RESET_REG_MISC_INT_STATUS);
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/* flush write */
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__raw_readl(base + AR71XX_RESET_REG_MISC_INT_STATUS);
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}
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static struct irq_chip ath79_misc_irq_chip = {
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.name = "MISC",
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.irq_unmask = ar71xx_misc_irq_unmask,
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.irq_mask = ar71xx_misc_irq_mask,
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};
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static void __init ath79_misc_irq_init(void)
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{
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void __iomem *base = ath79_reset_base;
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int i;
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__raw_writel(0, base + AR71XX_RESET_REG_MISC_INT_ENABLE);
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__raw_writel(0, base + AR71XX_RESET_REG_MISC_INT_STATUS);
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if (soc_is_ar71xx() || soc_is_ar913x())
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ath79_misc_irq_chip.irq_mask_ack = ar71xx_misc_irq_mask;
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else if (soc_is_ar724x() ||
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soc_is_ar933x() ||
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soc_is_ar934x() ||
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soc_is_qca955x())
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ath79_misc_irq_chip.irq_ack = ar724x_misc_irq_ack;
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else
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BUG();
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for (i = ATH79_MISC_IRQ_BASE;
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i < ATH79_MISC_IRQ_BASE + ATH79_MISC_IRQ_COUNT; i++) {
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irq_set_chip_and_handler(i, &ath79_misc_irq_chip,
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handle_level_irq);
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}
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irq_set_chained_handler(ATH79_CPU_IRQ(6), ath79_misc_irq_handler);
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}
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static void ar934x_ip2_irq_dispatch(unsigned int irq, struct irq_desc *desc)
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{
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u32 status;
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disable_irq_nosync(irq);
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status = ath79_reset_rr(AR934X_RESET_REG_PCIE_WMAC_INT_STATUS);
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if (status & AR934X_PCIE_WMAC_INT_PCIE_ALL) {
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ath79_ddr_wb_flush(3);
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generic_handle_irq(ATH79_IP2_IRQ(0));
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} else if (status & AR934X_PCIE_WMAC_INT_WMAC_ALL) {
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ath79_ddr_wb_flush(4);
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generic_handle_irq(ATH79_IP2_IRQ(1));
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} else {
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spurious_interrupt();
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}
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enable_irq(irq);
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}
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static void ar934x_ip2_irq_init(void)
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{
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int i;
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for (i = ATH79_IP2_IRQ_BASE;
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i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++)
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irq_set_chip_and_handler(i, &dummy_irq_chip,
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handle_level_irq);
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irq_set_chained_handler(ATH79_CPU_IRQ(2), ar934x_ip2_irq_dispatch);
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}
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static void qca955x_ip2_irq_dispatch(unsigned int irq, struct irq_desc *desc)
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{
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u32 status;
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disable_irq_nosync(irq);
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status = ath79_reset_rr(QCA955X_RESET_REG_EXT_INT_STATUS);
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status &= QCA955X_EXT_INT_PCIE_RC1_ALL | QCA955X_EXT_INT_WMAC_ALL;
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if (status == 0) {
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spurious_interrupt();
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goto enable;
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}
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if (status & QCA955X_EXT_INT_PCIE_RC1_ALL) {
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/* TODO: flush DDR? */
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generic_handle_irq(ATH79_IP2_IRQ(0));
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}
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if (status & QCA955X_EXT_INT_WMAC_ALL) {
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/* TODO: flush DDR? */
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generic_handle_irq(ATH79_IP2_IRQ(1));
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}
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enable:
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enable_irq(irq);
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}
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static void qca955x_ip3_irq_dispatch(unsigned int irq, struct irq_desc *desc)
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{
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u32 status;
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disable_irq_nosync(irq);
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status = ath79_reset_rr(QCA955X_RESET_REG_EXT_INT_STATUS);
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status &= QCA955X_EXT_INT_PCIE_RC2_ALL |
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QCA955X_EXT_INT_USB1 |
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QCA955X_EXT_INT_USB2;
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if (status == 0) {
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spurious_interrupt();
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goto enable;
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}
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if (status & QCA955X_EXT_INT_USB1) {
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/* TODO: flush DDR? */
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generic_handle_irq(ATH79_IP3_IRQ(0));
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}
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if (status & QCA955X_EXT_INT_USB2) {
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/* TODO: flush DDR? */
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generic_handle_irq(ATH79_IP3_IRQ(1));
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}
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if (status & QCA955X_EXT_INT_PCIE_RC2_ALL) {
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/* TODO: flush DDR? */
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generic_handle_irq(ATH79_IP3_IRQ(2));
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}
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enable:
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enable_irq(irq);
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}
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static void qca955x_irq_init(void)
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{
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int i;
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for (i = ATH79_IP2_IRQ_BASE;
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i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++)
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irq_set_chip_and_handler(i, &dummy_irq_chip,
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handle_level_irq);
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irq_set_chained_handler(ATH79_CPU_IRQ(2), qca955x_ip2_irq_dispatch);
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for (i = ATH79_IP3_IRQ_BASE;
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i < ATH79_IP3_IRQ_BASE + ATH79_IP3_IRQ_COUNT; i++)
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irq_set_chip_and_handler(i, &dummy_irq_chip,
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handle_level_irq);
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irq_set_chained_handler(ATH79_CPU_IRQ(3), qca955x_ip3_irq_dispatch);
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}
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/*
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* The IP2/IP3 lines are tied to a PCI/WMAC/USB device. Drivers for
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* these devices typically allocate coherent DMA memory, however the
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* DMA controller may still have some unsynchronized data in the FIFO.
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* Issue a flush in the handlers to ensure that the driver sees
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* the update.
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*
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* This array map the interrupt lines to the DDR write buffer channels.
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*/
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static unsigned irq_wb_chan[8] = {
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-1, -1, -1, -1, -1, -1, -1, -1,
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};
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asmlinkage void plat_irq_dispatch(void)
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{
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unsigned long pending;
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int irq;
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pending = read_c0_status() & read_c0_cause() & ST0_IM;
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if (!pending) {
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spurious_interrupt();
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return;
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}
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pending >>= CAUSEB_IP;
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while (pending) {
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irq = fls(pending) - 1;
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if (irq < ARRAY_SIZE(irq_wb_chan) && irq_wb_chan[irq] != -1)
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ath79_ddr_wb_flush(irq_wb_chan[irq]);
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do_IRQ(MIPS_CPU_IRQ_BASE + irq);
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pending &= ~BIT(irq);
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}
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}
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#ifdef CONFIG_IRQCHIP
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static int misc_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
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{
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irq_set_chip_and_handler(irq, &ath79_misc_irq_chip, handle_level_irq);
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return 0;
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}
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static const struct irq_domain_ops misc_irq_domain_ops = {
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.xlate = irq_domain_xlate_onecell,
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.map = misc_map,
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};
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static int __init ath79_misc_intc_of_init(
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struct device_node *node, struct device_node *parent)
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{
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void __iomem *base = ath79_reset_base;
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struct irq_domain *domain;
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int irq;
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irq = irq_of_parse_and_map(node, 0);
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if (!irq)
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panic("Failed to get MISC IRQ");
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domain = irq_domain_add_legacy(node, ATH79_MISC_IRQ_COUNT,
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ATH79_MISC_IRQ_BASE, 0, &misc_irq_domain_ops, NULL);
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if (!domain)
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panic("Failed to add MISC irqdomain");
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/* Disable and clear all interrupts */
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__raw_writel(0, base + AR71XX_RESET_REG_MISC_INT_ENABLE);
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__raw_writel(0, base + AR71XX_RESET_REG_MISC_INT_STATUS);
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irq_set_chained_handler(irq, ath79_misc_irq_handler);
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return 0;
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}
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IRQCHIP_DECLARE(ath79_misc_intc, "qca,ar7100-misc-intc",
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ath79_misc_intc_of_init);
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static int __init ar79_cpu_intc_of_init(
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struct device_node *node, struct device_node *parent)
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{
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int err, i, count;
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/* Fill the irq_wb_chan table */
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count = of_count_phandle_with_args(
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node, "qca,ddr-wb-channels", "#qca,ddr-wb-channel-cells");
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for (i = 0; i < count; i++) {
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struct of_phandle_args args;
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u32 irq = i;
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of_property_read_u32_index(
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node, "qca,ddr-wb-channel-interrupts", i, &irq);
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if (irq >= ARRAY_SIZE(irq_wb_chan))
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continue;
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err = of_parse_phandle_with_args(
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node, "qca,ddr-wb-channels",
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"#qca,ddr-wb-channel-cells",
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i, &args);
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if (err)
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return err;
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irq_wb_chan[irq] = args.args[0];
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pr_info("IRQ: Set flush channel of IRQ%d to %d\n",
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irq, args.args[0]);
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}
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return mips_cpu_irq_of_init(node, parent);
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}
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IRQCHIP_DECLARE(ar79_cpu_intc, "qca,ar7100-cpu-intc",
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ar79_cpu_intc_of_init);
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#endif
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void __init arch_init_irq(void)
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{
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if (mips_machtype == ATH79_MACH_GENERIC_OF) {
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irqchip_init();
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return;
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}
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if (soc_is_ar71xx() || soc_is_ar724x() ||
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soc_is_ar913x() || soc_is_ar933x()) {
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irq_wb_chan[2] = 3;
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irq_wb_chan[3] = 2;
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} else if (soc_is_ar934x()) {
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irq_wb_chan[3] = 2;
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}
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mips_cpu_irq_init();
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ath79_misc_irq_init();
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if (soc_is_ar934x())
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ar934x_ip2_irq_init();
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else if (soc_is_qca955x())
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qca955x_irq_init();
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}
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