forked from luck/tmp_suning_uos_patched
4508dc21fe
Currently the powerpc kernel has a 64-bit only feature, COHERENT_ICACHE used for those CPUS which maintain icache/dcache coherency in hardware (POWER5, essentially). It also has a feature, SPLIT_ID_CACHE, which is used on CPUs which have separate i and d-caches, which is to say everything except 601 and Freescale E200. In nearly all the places we check the SPLIT_ID_CACHE, what we actually care about is whether the i and d-caches are coherent (which they will be, trivially, if they're the same cache). This tries to clarify the situation a little. The COHERENT_ICACHE feature becomes availble on 32-bit and is set for all CPUs where i and d-cache are effectively coherent, whether this is due to special logic (POWER5) or because they're unified. We check this, instead of SPLIT_ID_CACHE nearly everywhere. The SPLIT_ID_CACHE feature itself is replaced by a UNIFIED_ID_CACHE feature with reversed sense, set only on 601 and Freescale E200. In the two places (one Freescale BookE specific) where we really care whether it's a unified cache, not whether they're coherent, we check this feature. The CPUs with unified cache are so few, we could consider replacing this feature bit with explicit checks against the PVR. This will make unifying the 32-bit and 64-bit cache flush code a little more straightforward. Signed-off-by: David Gibson <dwg@au1.ibm.com> Signed-off-by: Paul Mackerras <paulus@samba.org> |
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| .. | ||
| asm-offsets.c | ||
| cpu_setup_power4.S | ||
| entry.S | ||
| head_4xx.S | ||
| head_8xx.S | ||
| head_44x.S | ||
| head_booke.h | ||
| head_fsl_booke.S | ||
| head.S | ||
| machine_kexec.c | ||
| Makefile | ||
| misc.S | ||
| pci.c | ||
| ppc_htab.c | ||
| ppc_ksyms.c | ||
| ppc-stub.c | ||
| relocate_kernel.S | ||
| rio.c | ||
| semaphore.c | ||
| setup.c | ||
| smp-tbsync.c | ||
| smp.c | ||
| softemu8xx.c | ||
| time.c | ||
| traps.c | ||
| vmlinux.lds.S | ||