forked from luck/tmp_suning_uos_patched
f880c5649e
The existing MSM irq entry macro is specific to a VIC implementation. Renaming this makes room for irq support based on other interrupt controllers. Signed-off-by: Steve Muckle <smuckle@codeaurora.org> Signed-off-by: Daniel Walker <dwalker@codeaurora.org>
89 lines
2.6 KiB
ArmAsm
89 lines
2.6 KiB
ArmAsm
/*
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* Low-level IRQ helper macros
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*
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* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <mach/hardware.h>
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#include <asm/hardware/gic.h>
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.macro disable_fiq
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.endm
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.macro get_irqnr_preamble, base, tmp
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ldr \base, =gic_cpu_base_addr
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ldr \base, [\base]
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.endm
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.macro arch_ret_to_user, tmp1, tmp2
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.endm
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/*
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* The interrupt numbering scheme is defined in the
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* interrupt controller spec. To wit:
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*
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* Migrated the code from ARM MP port to be more consistant
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* with interrupt processing , the following still holds true
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* however, all interrupts are treated the same regardless of
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* if they are local IPI or PPI
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*
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* Interrupts 0-15 are IPI
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* 16-31 are PPI
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* (16-18 are the timers)
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* 32-1020 are global
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* 1021-1022 are reserved
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* 1023 is "spurious" (no interrupt)
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*
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* A simple read from the controller will tell us the number of the
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* highest priority enabled interrupt. We then just need to check
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* whether it is in the valid range for an IRQ (0-1020 inclusive).
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*
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* Base ARM code assumes that the local (private) peripheral interrupts
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* are not valid, we treat them differently, in that the privates are
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* handled like normal shared interrupts with the exception that only
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* one processor can register the interrupt and the handler must be
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* the same for all processors.
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*/
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.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
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ldr \irqstat, [\base, #GIC_CPU_INTACK] /* bits 12-10 =srcCPU,
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9-0 =int # */
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bic \irqnr, \irqstat, #0x1c00 @mask src
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cmp \irqnr, #15
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ldr \tmp, =1021
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cmpcc \irqnr, \irqnr
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cmpne \irqnr, \tmp
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cmpcs \irqnr, \irqnr
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.endm
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/* We assume that irqstat (the raw value of the IRQ acknowledge
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* register) is preserved from the macro above.
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* If there is an IPI, we immediately signal end of interrupt on the
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* controller, since this requires the original irqstat value which
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* we won't easily be able to recreate later.
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*/
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.macro test_for_ipi, irqnr, irqstat, base, tmp
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bic \irqnr, \irqstat, #0x1c00
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cmp \irqnr, #16
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strcc \irqstat, [\base, #GIC_CPU_EOI]
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cmpcs \irqnr, \irqnr
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.endm
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/* As above, this assumes that irqstat and base are preserved.. */
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.macro test_for_ltirq, irqnr, irqstat, base, tmp
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bic \irqnr, \irqstat, #0x1c00
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mov \tmp, #0
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cmp \irqnr, #16
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moveq \tmp, #1
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streq \irqstat, [\base, #GIC_CPU_EOI]
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cmp \tmp, #0
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.endm
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