forked from luck/tmp_suning_uos_patched
04896a77a9
Signed-off-by: Brian Swetland <swetland@google.com> Signed-off-by: Alan Cox <alan@linux.intel.com> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
118 lines
3.5 KiB
C
118 lines
3.5 KiB
C
/*
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* drivers/serial/msm_serial.h
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*
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* Copyright (C) 2007 Google, Inc.
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* Author: Robert Love <rlove@google.com>
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef __DRIVERS_SERIAL_MSM_SERIAL_H
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#define __DRIVERS_SERIAL_MSM_SERIAL_H
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#define UART_MR1 0x0000
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#define UART_MR1_AUTO_RFR_LEVEL0 0x3F
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#define UART_MR1_AUTO_RFR_LEVEL1 0x3FF00
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#define UART_MR1_RX_RDY_CTL (1 << 7)
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#define UART_MR1_CTS_CTL (1 << 6)
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#define UART_MR2 0x0004
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#define UART_MR2_ERROR_MODE (1 << 6)
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#define UART_MR2_BITS_PER_CHAR 0x30
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#define UART_MR2_BITS_PER_CHAR_5 (0x0 << 4)
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#define UART_MR2_BITS_PER_CHAR_6 (0x1 << 4)
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#define UART_MR2_BITS_PER_CHAR_7 (0x2 << 4)
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#define UART_MR2_BITS_PER_CHAR_8 (0x3 << 4)
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#define UART_MR2_STOP_BIT_LEN_ONE (0x1 << 2)
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#define UART_MR2_STOP_BIT_LEN_TWO (0x3 << 2)
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#define UART_MR2_PARITY_MODE_NONE 0x0
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#define UART_MR2_PARITY_MODE_ODD 0x1
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#define UART_MR2_PARITY_MODE_EVEN 0x2
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#define UART_MR2_PARITY_MODE_SPACE 0x3
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#define UART_MR2_PARITY_MODE 0x3
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#define UART_CSR 0x0008
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#define UART_CSR_115200 0xFF
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#define UART_CSR_57600 0xEE
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#define UART_CSR_38400 0xDD
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#define UART_CSR_28800 0xCC
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#define UART_CSR_19200 0xBB
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#define UART_CSR_14400 0xAA
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#define UART_CSR_9600 0x99
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#define UART_CSR_4800 0x77
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#define UART_CSR_2400 0x55
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#define UART_CSR_1200 0x44
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#define UART_CSR_600 0x33
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#define UART_CSR_300 0x22
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#define UART_TF 0x000C
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#define UART_CR 0x0010
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#define UART_CR_CMD_NULL (0 << 4)
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#define UART_CR_CMD_RESET_RX (1 << 4)
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#define UART_CR_CMD_RESET_TX (2 << 4)
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#define UART_CR_CMD_RESET_ERR (3 << 4)
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#define UART_CR_CMD_RESET_BREAK_INT (4 << 4)
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#define UART_CR_CMD_START_BREAK (5 << 4)
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#define UART_CR_CMD_STOP_BREAK (6 << 4)
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#define UART_CR_CMD_RESET_CTS (7 << 4)
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#define UART_CR_CMD_PACKET_MODE (9 << 4)
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#define UART_CR_CMD_MODE_RESET (12 << 4)
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#define UART_CR_CMD_SET_RFR (13 << 4)
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#define UART_CR_CMD_RESET_RFR (14 << 4)
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#define UART_CR_TX_DISABLE (1 << 3)
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#define UART_CR_TX_ENABLE (1 << 3)
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#define UART_CR_RX_DISABLE (1 << 3)
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#define UART_CR_RX_ENABLE (1 << 3)
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#define UART_IMR 0x0014
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#define UART_IMR_TXLEV (1 << 0)
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#define UART_IMR_RXSTALE (1 << 3)
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#define UART_IMR_RXLEV (1 << 4)
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#define UART_IMR_DELTA_CTS (1 << 5)
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#define UART_IMR_CURRENT_CTS (1 << 6)
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#define UART_IPR_RXSTALE_LAST 0x20
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#define UART_IPR_STALE_LSB 0x1F
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#define UART_IPR_STALE_TIMEOUT_MSB 0x3FF80
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#define UART_IPR 0x0018
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#define UART_TFWR 0x001C
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#define UART_RFWR 0x0020
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#define UART_HCR 0x0024
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#define UART_MREG 0x0028
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#define UART_NREG 0x002C
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#define UART_DREG 0x0030
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#define UART_MNDREG 0x0034
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#define UART_IRDA 0x0038
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#define UART_MISR_MODE 0x0040
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#define UART_MISR_RESET 0x0044
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#define UART_MISR_EXPORT 0x0048
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#define UART_MISR_VAL 0x004C
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#define UART_TEST_CTRL 0x0050
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#define UART_SR 0x0008
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#define UART_SR_HUNT_CHAR (1 << 7)
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#define UART_SR_RX_BREAK (1 << 6)
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#define UART_SR_PAR_FRAME_ERR (1 << 5)
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#define UART_SR_OVERRUN (1 << 4)
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#define UART_SR_TX_EMPTY (1 << 3)
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#define UART_SR_TX_READY (1 << 2)
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#define UART_SR_RX_FULL (1 << 1)
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#define UART_SR_RX_READY (1 << 0)
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#define UART_RF 0x000C
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#define UART_MISR 0x0010
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#define UART_ISR 0x0014
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#endif /* __DRIVERS_SERIAL_MSM_SERIAL_H */
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