forked from luck/tmp_suning_uos_patched
6ebbf2ce43
ARMv6 and greater introduced a new instruction ("bx") which can be used
to return from function calls. Recent CPUs perform better when the
"bx lr" instruction is used rather than the "mov pc, lr" instruction,
and this sequence is strongly recommended to be used by the ARM
architecture manual (section A.4.1.1).
We provide a new macro "ret" with all its variants for the condition
code which will resolve to the appropriate instruction.
Rather than doing this piecemeal, and miss some instances, change all
the "mov pc" instances to use the new macro, with the exception of
the "movs" instruction and the kprobes code. This allows us to detect
the "mov pc, lr" case and fix it up - and also gives us the possibility
of deploying this for other registers depending on the CPU selection.
Reported-by: Will Deacon <will.deacon@arm.com>
Tested-by: Stephen Warren <swarren@nvidia.com> # Tegra Jetson TK1
Tested-by: Robert Jarzmik <robert.jarzmik@free.fr> # mioa701_bootresume.S
Tested-by: Andrew Lunn <andrew@lunn.ch> # Kirkwood
Tested-by: Shawn Guo <shawn.guo@freescale.com>
Tested-by: Tony Lindgren <tony@atomide.com> # OMAPs
Tested-by: Gregory CLEMENT <gregory.clement@free-electrons.com> # Armada XP, 375, 385
Acked-by: Sekhar Nori <nsekhar@ti.com> # DaVinci
Acked-by: Christoffer Dall <christoffer.dall@linaro.org> # kvm/hyp
Acked-by: Haojian Zhuang <haojian.zhuang@gmail.com> # PXA3xx
Acked-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com> # Xen
Tested-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> # ARMv7M
Tested-by: Simon Horman <horms+renesas@verge.net.au> # Shmobile
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
251 lines
6.1 KiB
ArmAsm
251 lines
6.1 KiB
ArmAsm
/*
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* linux/arch/arm/mm/cache-fa.S
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*
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* Copyright (C) 2005 Faraday Corp.
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* Copyright (C) 2008-2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
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*
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* Based on cache-v4wb.S:
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* Copyright (C) 1997-2002 Russell king
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* Processors: FA520 FA526 FA626
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*/
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#include <linux/linkage.h>
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#include <linux/init.h>
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#include <asm/assembler.h>
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#include <asm/memory.h>
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#include <asm/page.h>
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#include "proc-macros.S"
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/*
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* The size of one data cache line.
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*/
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#define CACHE_DLINESIZE 16
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/*
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* The total size of the data cache.
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*/
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#ifdef CONFIG_ARCH_GEMINI
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#define CACHE_DSIZE 8192
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#else
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#define CACHE_DSIZE 16384
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#endif
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/* FIXME: put optimal value here. Current one is just estimation */
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#define CACHE_DLIMIT (CACHE_DSIZE * 2)
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/*
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* flush_icache_all()
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*
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* Unconditionally clean and invalidate the entire icache.
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*/
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ENTRY(fa_flush_icache_all)
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mov r0, #0
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mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
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ret lr
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ENDPROC(fa_flush_icache_all)
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/*
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* flush_user_cache_all()
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*
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* Clean and invalidate all cache entries in a particular address
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* space.
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*/
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ENTRY(fa_flush_user_cache_all)
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/* FALLTHROUGH */
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/*
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* flush_kern_cache_all()
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*
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* Clean and invalidate the entire cache.
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*/
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ENTRY(fa_flush_kern_cache_all)
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mov ip, #0
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mov r2, #VM_EXEC
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__flush_whole_cache:
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mcr p15, 0, ip, c7, c14, 0 @ clean/invalidate D cache
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tst r2, #VM_EXEC
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mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
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mcrne p15, 0, ip, c7, c5, 6 @ invalidate BTB
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mcrne p15, 0, ip, c7, c10, 4 @ drain write buffer
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mcrne p15, 0, ip, c7, c5, 4 @ prefetch flush
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ret lr
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/*
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* flush_user_cache_range(start, end, flags)
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*
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* Invalidate a range of cache entries in the specified
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* address space.
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*
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* - start - start address (inclusive, page aligned)
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* - end - end address (exclusive, page aligned)
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* - flags - vma_area_struct flags describing address space
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*/
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ENTRY(fa_flush_user_cache_range)
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mov ip, #0
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sub r3, r1, r0 @ calculate total size
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cmp r3, #CACHE_DLIMIT @ total size >= limit?
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bhs __flush_whole_cache @ flush whole D cache
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1: tst r2, #VM_EXEC
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mcrne p15, 0, r0, c7, c5, 1 @ invalidate I line
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mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
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add r0, r0, #CACHE_DLINESIZE
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cmp r0, r1
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blo 1b
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tst r2, #VM_EXEC
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mcrne p15, 0, ip, c7, c5, 6 @ invalidate BTB
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mcrne p15, 0, ip, c7, c10, 4 @ data write barrier
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mcrne p15, 0, ip, c7, c5, 4 @ prefetch flush
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ret lr
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/*
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* coherent_kern_range(start, end)
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*
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* Ensure coherency between the Icache and the Dcache in the
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* region described by start. If you have non-snooping
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* Harvard caches, you need to implement this function.
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*
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* - start - virtual start address
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* - end - virtual end address
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*/
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ENTRY(fa_coherent_kern_range)
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/* fall through */
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/*
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* coherent_user_range(start, end)
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*
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* Ensure coherency between the Icache and the Dcache in the
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* region described by start. If you have non-snooping
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* Harvard caches, you need to implement this function.
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*
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* - start - virtual start address
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* - end - virtual end address
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*/
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ENTRY(fa_coherent_user_range)
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bic r0, r0, #CACHE_DLINESIZE - 1
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1: mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
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mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
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add r0, r0, #CACHE_DLINESIZE
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cmp r0, r1
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blo 1b
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mov r0, #0
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mcr p15, 0, r0, c7, c5, 6 @ invalidate BTB
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mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
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mcr p15, 0, r0, c7, c5, 4 @ prefetch flush
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ret lr
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/*
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* flush_kern_dcache_area(void *addr, size_t size)
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*
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* Ensure that the data held in the page kaddr is written back
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* to the page in question.
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*
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* - addr - kernel address
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* - size - size of region
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*/
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ENTRY(fa_flush_kern_dcache_area)
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add r1, r0, r1
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1: mcr p15, 0, r0, c7, c14, 1 @ clean & invalidate D line
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add r0, r0, #CACHE_DLINESIZE
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cmp r0, r1
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blo 1b
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mov r0, #0
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mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
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mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
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ret lr
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/*
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* dma_inv_range(start, end)
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*
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* Invalidate (discard) the specified virtual address range.
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* May not write back any entries. If 'start' or 'end'
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* are not cache line aligned, those lines must be written
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* back.
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*
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* - start - virtual start address
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* - end - virtual end address
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*/
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fa_dma_inv_range:
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tst r0, #CACHE_DLINESIZE - 1
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bic r0, r0, #CACHE_DLINESIZE - 1
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mcrne p15, 0, r0, c7, c14, 1 @ clean & invalidate D entry
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tst r1, #CACHE_DLINESIZE - 1
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bic r1, r1, #CACHE_DLINESIZE - 1
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mcrne p15, 0, r1, c7, c14, 1 @ clean & invalidate D entry
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1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
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add r0, r0, #CACHE_DLINESIZE
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cmp r0, r1
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blo 1b
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mov r0, #0
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mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
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ret lr
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/*
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* dma_clean_range(start, end)
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*
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* Clean (write back) the specified virtual address range.
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*
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* - start - virtual start address
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* - end - virtual end address
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*/
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fa_dma_clean_range:
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bic r0, r0, #CACHE_DLINESIZE - 1
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1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
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add r0, r0, #CACHE_DLINESIZE
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cmp r0, r1
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blo 1b
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mov r0, #0
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mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
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ret lr
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/*
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* dma_flush_range(start,end)
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* - start - virtual start address of region
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* - end - virtual end address of region
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*/
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ENTRY(fa_dma_flush_range)
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bic r0, r0, #CACHE_DLINESIZE - 1
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1: mcr p15, 0, r0, c7, c14, 1 @ clean & invalidate D entry
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add r0, r0, #CACHE_DLINESIZE
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cmp r0, r1
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blo 1b
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mov r0, #0
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mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
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ret lr
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/*
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* dma_map_area(start, size, dir)
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* - start - kernel virtual start address
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* - size - size of region
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* - dir - DMA direction
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*/
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ENTRY(fa_dma_map_area)
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add r1, r1, r0
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cmp r2, #DMA_TO_DEVICE
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beq fa_dma_clean_range
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bcs fa_dma_inv_range
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b fa_dma_flush_range
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ENDPROC(fa_dma_map_area)
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/*
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* dma_unmap_area(start, size, dir)
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* - start - kernel virtual start address
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* - size - size of region
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* - dir - DMA direction
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*/
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ENTRY(fa_dma_unmap_area)
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ret lr
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ENDPROC(fa_dma_unmap_area)
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.globl fa_flush_kern_cache_louis
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.equ fa_flush_kern_cache_louis, fa_flush_kern_cache_all
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__INITDATA
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@ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S)
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define_cache_functions fa
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