forked from luck/tmp_suning_uos_patched
f4e4c324a5
This patch syncs omap specific headers with linux-omap. Most of the changes needed because of bitrot caused by driver changes in linux-omap tree. Integrating this is needed for adding support for various omap drivers. Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
198 lines
8.2 KiB
C
198 lines
8.2 KiB
C
/* linux/include/asm-arm/arch-omap/omap16xx.h
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*
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* Hardware definitions for TI OMAP1610/5912/1710 processors.
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*
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* Cleanup for Linux-2.6 by Dirk Behme <dirk.behme@de.bosch.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
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* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
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* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#ifndef __ASM_ARCH_OMAP16XX_H
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#define __ASM_ARCH_OMAP16XX_H
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/*
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* ----------------------------------------------------------------------------
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* Base addresses
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* ----------------------------------------------------------------------------
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*/
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/* Syntax: XX_BASE = Virtual base address, XX_START = Physical base address */
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#define OMAP16XX_DSP_BASE 0xE0000000
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#define OMAP16XX_DSP_SIZE 0x28000
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#define OMAP16XX_DSP_START 0xE0000000
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#define OMAP16XX_DSPREG_BASE 0xE1000000
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#define OMAP16XX_DSPREG_SIZE SZ_128K
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#define OMAP16XX_DSPREG_START 0xE1000000
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/*
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* ---------------------------------------------------------------------------
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* Interrupts
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* ---------------------------------------------------------------------------
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*/
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#define OMAP_IH2_0_BASE (0xfffe0000)
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#define OMAP_IH2_1_BASE (0xfffe0100)
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#define OMAP_IH2_2_BASE (0xfffe0200)
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#define OMAP_IH2_3_BASE (0xfffe0300)
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#define OMAP_IH2_0_ITR (OMAP_IH2_0_BASE + 0x00)
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#define OMAP_IH2_0_MIR (OMAP_IH2_0_BASE + 0x04)
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#define OMAP_IH2_0_SIR_IRQ (OMAP_IH2_0_BASE + 0x10)
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#define OMAP_IH2_0_SIR_FIQ (OMAP_IH2_0_BASE + 0x14)
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#define OMAP_IH2_0_CONTROL (OMAP_IH2_0_BASE + 0x18)
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#define OMAP_IH2_0_ILR0 (OMAP_IH2_0_BASE + 0x1c)
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#define OMAP_IH2_0_ISR (OMAP_IH2_0_BASE + 0x9c)
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#define OMAP_IH2_1_ITR (OMAP_IH2_1_BASE + 0x00)
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#define OMAP_IH2_1_MIR (OMAP_IH2_1_BASE + 0x04)
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#define OMAP_IH2_1_SIR_IRQ (OMAP_IH2_1_BASE + 0x10)
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#define OMAP_IH2_1_SIR_FIQ (OMAP_IH2_1_BASE + 0x14)
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#define OMAP_IH2_1_CONTROL (OMAP_IH2_1_BASE + 0x18)
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#define OMAP_IH2_1_ILR1 (OMAP_IH2_1_BASE + 0x1c)
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#define OMAP_IH2_1_ISR (OMAP_IH2_1_BASE + 0x9c)
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#define OMAP_IH2_2_ITR (OMAP_IH2_2_BASE + 0x00)
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#define OMAP_IH2_2_MIR (OMAP_IH2_2_BASE + 0x04)
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#define OMAP_IH2_2_SIR_IRQ (OMAP_IH2_2_BASE + 0x10)
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#define OMAP_IH2_2_SIR_FIQ (OMAP_IH2_2_BASE + 0x14)
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#define OMAP_IH2_2_CONTROL (OMAP_IH2_2_BASE + 0x18)
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#define OMAP_IH2_2_ILR2 (OMAP_IH2_2_BASE + 0x1c)
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#define OMAP_IH2_2_ISR (OMAP_IH2_2_BASE + 0x9c)
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#define OMAP_IH2_3_ITR (OMAP_IH2_3_BASE + 0x00)
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#define OMAP_IH2_3_MIR (OMAP_IH2_3_BASE + 0x04)
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#define OMAP_IH2_3_SIR_IRQ (OMAP_IH2_3_BASE + 0x10)
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#define OMAP_IH2_3_SIR_FIQ (OMAP_IH2_3_BASE + 0x14)
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#define OMAP_IH2_3_CONTROL (OMAP_IH2_3_BASE + 0x18)
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#define OMAP_IH2_3_ILR3 (OMAP_IH2_3_BASE + 0x1c)
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#define OMAP_IH2_3_ISR (OMAP_IH2_3_BASE + 0x9c)
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/*
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* ----------------------------------------------------------------------------
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* Clocks
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* ----------------------------------------------------------------------------
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*/
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#define OMAP16XX_ARM_IDLECT3 (CLKGEN_REG_BASE + 0x24)
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/*
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* ----------------------------------------------------------------------------
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* Pin configuration registers
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* ----------------------------------------------------------------------------
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*/
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#define OMAP16XX_CONF_VOLTAGE_VDDSHV6 (1 << 8)
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#define OMAP16XX_CONF_VOLTAGE_VDDSHV7 (1 << 9)
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#define OMAP16XX_CONF_VOLTAGE_VDDSHV8 (1 << 10)
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#define OMAP16XX_CONF_VOLTAGE_VDDSHV9 (1 << 11)
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#define OMAP16XX_SUBLVDS_CONF_VALID (1 << 13)
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/*
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* ----------------------------------------------------------------------------
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* System control registers
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* ----------------------------------------------------------------------------
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*/
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#define OMAP1610_RESET_CONTROL 0xfffe1140
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/*
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* ---------------------------------------------------------------------------
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* TIPB bus interface
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* ---------------------------------------------------------------------------
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*/
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#define TIPB_SWITCH_BASE (0xfffbc800)
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#define OMAP16XX_MMCSD2_SSW_MPU_CONF (TIPB_SWITCH_BASE + 0x160)
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/* UART3 Registers Maping through MPU bus */
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#define UART3_RHR (OMAP_UART3_BASE + 0)
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#define UART3_THR (OMAP_UART3_BASE + 0)
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#define UART3_DLL (OMAP_UART3_BASE + 0)
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#define UART3_IER (OMAP_UART3_BASE + 4)
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#define UART3_DLH (OMAP_UART3_BASE + 4)
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#define UART3_IIR (OMAP_UART3_BASE + 8)
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#define UART3_FCR (OMAP_UART3_BASE + 8)
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#define UART3_EFR (OMAP_UART3_BASE + 8)
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#define UART3_LCR (OMAP_UART3_BASE + 0x0C)
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#define UART3_MCR (OMAP_UART3_BASE + 0x10)
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#define UART3_XON1_ADDR1 (OMAP_UART3_BASE + 0x10)
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#define UART3_XON2_ADDR2 (OMAP_UART3_BASE + 0x14)
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#define UART3_LSR (OMAP_UART3_BASE + 0x14)
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#define UART3_TCR (OMAP_UART3_BASE + 0x18)
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#define UART3_MSR (OMAP_UART3_BASE + 0x18)
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#define UART3_XOFF1 (OMAP_UART3_BASE + 0x18)
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#define UART3_XOFF2 (OMAP_UART3_BASE + 0x1C)
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#define UART3_SPR (OMAP_UART3_BASE + 0x1C)
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#define UART3_TLR (OMAP_UART3_BASE + 0x1C)
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#define UART3_MDR1 (OMAP_UART3_BASE + 0x20)
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#define UART3_MDR2 (OMAP_UART3_BASE + 0x24)
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#define UART3_SFLSR (OMAP_UART3_BASE + 0x28)
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#define UART3_TXFLL (OMAP_UART3_BASE + 0x28)
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#define UART3_RESUME (OMAP_UART3_BASE + 0x2C)
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#define UART3_TXFLH (OMAP_UART3_BASE + 0x2C)
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#define UART3_SFREGL (OMAP_UART3_BASE + 0x30)
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#define UART3_RXFLL (OMAP_UART3_BASE + 0x30)
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#define UART3_SFREGH (OMAP_UART3_BASE + 0x34)
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#define UART3_RXFLH (OMAP_UART3_BASE + 0x34)
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#define UART3_BLR (OMAP_UART3_BASE + 0x38)
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#define UART3_ACREG (OMAP_UART3_BASE + 0x3C)
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#define UART3_DIV16 (OMAP_UART3_BASE + 0x3C)
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#define UART3_SCR (OMAP_UART3_BASE + 0x40)
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#define UART3_SSR (OMAP_UART3_BASE + 0x44)
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#define UART3_EBLR (OMAP_UART3_BASE + 0x48)
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#define UART3_OSC_12M_SEL (OMAP_UART3_BASE + 0x4C)
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#define UART3_MVR (OMAP_UART3_BASE + 0x50)
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/*
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* ---------------------------------------------------------------------------
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* Watchdog timer
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* ---------------------------------------------------------------------------
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*/
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/* 32-bit Watchdog timer in OMAP 16XX */
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#define OMAP_16XX_WATCHDOG_BASE (0xfffeb000)
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#define OMAP_16XX_WIDR (OMAP_16XX_WATCHDOG_BASE + 0x00)
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#define OMAP_16XX_WD_SYSCONFIG (OMAP_16XX_WATCHDOG_BASE + 0x10)
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#define OMAP_16XX_WD_SYSSTATUS (OMAP_16XX_WATCHDOG_BASE + 0x14)
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#define OMAP_16XX_WCLR (OMAP_16XX_WATCHDOG_BASE + 0x24)
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#define OMAP_16XX_WCRR (OMAP_16XX_WATCHDOG_BASE + 0x28)
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#define OMAP_16XX_WLDR (OMAP_16XX_WATCHDOG_BASE + 0x2c)
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#define OMAP_16XX_WTGR (OMAP_16XX_WATCHDOG_BASE + 0x30)
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#define OMAP_16XX_WWPS (OMAP_16XX_WATCHDOG_BASE + 0x34)
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#define OMAP_16XX_WSPR (OMAP_16XX_WATCHDOG_BASE + 0x48)
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#define WCLR_PRE_SHIFT 5
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#define WCLR_PTV_SHIFT 2
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#define WWPS_W_PEND_WSPR (1 << 4)
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#define WWPS_W_PEND_WTGR (1 << 3)
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#define WWPS_W_PEND_WLDR (1 << 2)
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#define WWPS_W_PEND_WCRR (1 << 1)
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#define WWPS_W_PEND_WCLR (1 << 0)
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#define WSPR_ENABLE_0 (0x0000bbbb)
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#define WSPR_ENABLE_1 (0x00004444)
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#define WSPR_DISABLE_0 (0x0000aaaa)
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#define WSPR_DISABLE_1 (0x00005555)
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/* Mailbox */
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#define OMAP16XX_MAILBOX_BASE (0xfffcf000)
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#endif /* __ASM_ARCH_OMAP16XX_H */
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