forked from luck/tmp_suning_uos_patched
585cf17561
The Marvell Orion is a family of ARM SoCs with a DDR/DDR2 memory controller, 10/100/1000 ethernet MAC, and USB 2.0 interfaces, and, depending on the specific model, PCI-E interface, PCI-X interface, SATA controllers, crypto unit, SPI interface, SDIO interface, device bus, NAND controller, DMA engine and/or XOR engine. This contains the basic structure and architecture register definitions. Signed-off-by: Tzachi Perelstein <tzachi@marvell.com> Reviewed-by: Nicolas Pitre <nico@marvell.com> Reviewed-by: Lennert Buytenhek <buytenh@marvell.com> Acked-by: Russell King <rmk+kernel@arm.linux.org.uk>
32 lines
834 B
ArmAsm
32 lines
834 B
ArmAsm
/*
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* include/asm-arm/arch-orion/entry-macro.S
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*
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* Low-level IRQ helper macros for Orion platforms
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <asm/arch/orion.h>
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.macro disable_fiq
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.endm
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.macro arch_ret_to_user, tmp1, tmp2
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.endm
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.macro get_irqnr_preamble, base, tmp
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ldr \base, =MAIN_IRQ_CAUSE
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.endm
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.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
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ldr \irqstat, [\base, #0] @ main cause
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ldr \tmp, [\base, #(MAIN_IRQ_MASK - MAIN_IRQ_CAUSE)] @ main mask
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mov \irqnr, #0 @ default irqnr
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@ find cause bits that are unmasked
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ands \irqstat, \irqstat, \tmp @ clear Z flag if any
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clzne \irqnr, \irqstat @ calc irqnr
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rsbne \irqnr, \irqnr, #31
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.endm
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