kernel_optimize_test/drivers/clk/rockchip
Linus Torvalds 3fec0eaaf0 This pull request contains zero diff to the core framework. It is a collection
of various clk driver updates. The biggest driver updates in terms of lines of
 code is the Allwinner driver, closely followed by the Qualcomm and Mediatek
 drivers. All of those hit high because we add so many lines of clk data. Coming
 in fourth place is i.MX which also adds a bunch of clk data. This accounts for
 the new driver additions this time around.
 
 Otherwise the patches are lots of little cleanups and fixes for various clk
 drivers that have baked in linux-next for a while. I suppose one highlight or
 theme is that more clk drivers are being updated to work as modules, which is
 interesting to see such critical SoC infrastructure work as a loadable module.
 
 New Drivers:
  - Support qcom SM8150/SM8250 video and display clks
  - Support Mediatek MT8167 clks
  - Add clock for CRC block found on vf610 SoCs
  - Add support for the Renesas R-Car V3U (R8A779A0) SoC
  - Add support for the VSP for Resizing clock on Renesas RZ/G1H
  - Support Allwinner A100 SoC clks
 
 Removed Drivers:
  - Remove i.MX21 clock driver, as i.MX21 platform support is being dropped
 
 Updates:
  - Change how qcom's display port clks work
  - Small non-critical fixes for TI clk driver
  - Remove various unused variables in clk drivers
  - Allow Rockchip clk driver to be a module
  - Remove most __clk_lookup() calls in Samsung drivers (yay!)
  - Support building i.MX ARMv8 platforms clock driver as module
  - Some kerneldoc fixes here and there
  - A couple of minor i.MX clk data corrections
  - Update audio clock inverter and fdiv2 flag on Amlogic g12
  - Make amlogic clk drivers configurable in Kconfig
  - Fix Renesas VSP clock names to match corrected hardware documentation
  - Sigma-delta modulation on Allwinner R40
  - Various fixes for at91 clk driver
  - Use semicolons instead of commas in some places
  - Mark some variables const so they can move to RO memory
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Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux

Pull clk updates from Stephen Boyd:
 "This contains no changes to the core framework. It is a collection of
  various clk driver updates.

  The biggest driver updates in terms of lines of code is the Allwinner
  driver, closely followed by the Qualcomm and Mediatek drivers. All of
  those hit high because we add so many lines of clk data. Coming in
  fourth place is i.MX which also adds a bunch of clk data. This
  accounts for the new driver additions this time around.

  Otherwise the patches are lots of little cleanups and fixes for
  various clk drivers that have baked in linux-next for a while. I
  suppose one highlight or theme is that more clk drivers are being
  updated to work as modules, which is interesting to see such critical
  SoC infrastructure work as a loadable module.

  New Drivers:
   - Support qcom SM8150/SM8250 video and display clks
   - Support Mediatek MT8167 clks
   - Add clock for CRC block found on vf610 SoCs
   - Add support for the Renesas R-Car V3U (R8A779A0) SoC
   - Add support for the VSP for Resizing clock on Renesas RZ/G1H
   - Support Allwinner A100 SoC clks

  Removed Drivers:
   - Remove i.MX21 clock driver, as i.MX21 platform support is being
     dropped

  Updates:
   - Change how qcom's display port clks work
   - Small non-critical fixes for TI clk driver
   - Remove various unused variables in clk drivers
   - Allow Rockchip clk driver to be a module
   - Remove most __clk_lookup() calls in Samsung drivers (yay!)
   - Support building i.MX ARMv8 platforms clock driver as module
   - Some kerneldoc fixes here and there
   - A couple of minor i.MX clk data corrections
   - Update audio clock inverter and fdiv2 flag on Amlogic g12
   - Make amlogic clk drivers configurable in Kconfig
   - Fix Renesas VSP clock names to match corrected hardware
     documentation
   - Sigma-delta modulation on Allwinner R40
   - Various fixes for at91 clk driver
   - Use semicolons instead of commas in some places
   - Mark some variables const so they can move to RO memory"

* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (102 commits)
  clk: imx8mq: Fix usdhc parents order
  clk: qcom: gdsc: Keep RETAIN_FF bit set if gdsc is already on
  clk: Restrict CLK_HSDK to ARC_SOC_HSDK
  clk: at91: sam9x60: support only two programmable clocks
  clk: ingenic: Respect CLK_SET_RATE_PARENT in .round_rate
  clk: ingenic: Don't tag custom clocks with CLK_SET_RATE_PARENT
  clk: ingenic: Don't use CLK_SET_RATE_GATE for PLL
  clk: ingenic: Use readl_poll_timeout instead of custom loop
  clk: ingenic: Use to_clk_info() macro for all clocks
  clk: bcm2835: add missing release if devm_clk_hw_register fails
  clk: at91: clk-sam9x60-pll: remove unused variable
  clk: at91: clk-main: update key before writing AT91_CKGR_MOR
  clk: at91: remove the checking of parent_name
  clk: clk-prima2: fix return value check in prima2_clk_init()
  clk: mmp2: Fix the display clock divider base
  clk: pxa: Constify static struct clk_ops
  clk: baikal-t1: Mark Ethernet PLL as critical
  clk: qoriq: modify MAX_PLL_DIV to 32
  clk: axi-clkgen: Set power bits for fractional mode
  clk: axi-clkgen: Add support for fractional dividers
  ...
2020-10-22 12:53:28 -07:00
..
clk-cpu.c treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500 2019-06-19 17:09:55 +02:00
clk-ddr.c clk: rockchip: Export rockchip_clk_register_ddrclk() 2020-09-22 15:16:37 +02:00
clk-half-divider.c clk: rockchip: Initialize hw to error to avoid undefined behavior 2020-10-07 19:08:38 -07:00
clk-inverter.c treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 157 2019-05-30 11:26:37 -07:00
clk-mmc-phase.c clk: rockchip: fix mmc get phase 2020-03-06 12:06:01 -08:00
clk-muxgrf.c treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 282 2019-06-05 17:36:37 +02:00
clk-pll.c clk: rockchip: convert rk3036 pll type to use internal lock status 2020-06-15 11:47:16 +02:00
clk-px30.c clk: rockchip: protect the pclk_usb_grf as critical on px30 2019-11-05 20:53:42 +01:00
clk-rk3036.c treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 157 2019-05-30 11:26:37 -07:00
clk-rk3128.c treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 157 2019-05-30 11:26:37 -07:00
clk-rk3188.c clk: rockchip: add sclk_mac_lbtest to rk3188_critical_clocks 2020-07-22 20:05:19 +02:00
clk-rk3228.c clk: rockchip: Fix initialization of mux_pll_src_4plls_p 2020-08-18 20:09:02 -07:00
clk-rk3288.c clk: rockchip: use separate compatibles for rk3288w-cru 2020-07-05 12:18:29 +02:00
clk-rk3308.c clk: rockchip: rk3308: drop unused mux_timer_src_p 2020-09-22 14:36:20 +02:00
clk-rk3328.c clk: rockchip: Revert "fix wrong mmc sample phase shift for rk3328" 2020-07-08 16:22:10 +02:00
clk-rk3368.c This round of clk driver and framework updates is heavy on the driver update 2019-07-17 10:07:48 -07:00
clk-rk3399.c clk: rockchip: rk3399: Support module build 2020-09-22 15:16:54 +02:00
clk-rv1108.c clk: rockchip: Fix -Wunused-const-variable in rv1108 clk driver 2019-07-25 21:00:52 +02:00
clk.c clk: rockchip: Export some clock common APIs for module drivers 2020-09-22 15:16:38 +02:00
clk.h clk: rockchip: Add clock controller for the rk3308 2019-09-05 12:43:39 +02:00
Kconfig clk: rockchip: rk3399: Support module build 2020-09-22 15:16:54 +02:00
Makefile clk: rockchip: fix the clk config to support module build 2020-09-22 15:16:38 +02:00
softrst.c clk: rockchip: Export rockchip_register_softrst() 2020-09-22 15:16:38 +02:00