forked from luck/tmp_suning_uos_patched
2153bbc12f
According to the datasheet the update bit must be set if the on-time-div or the base-unit changes. Now that we properly order device resume on Cherry Trail so that the GFX0 _PS0 method no longer exits with an error, we end up with a sequence of events where we are writing the same values twice in a row. First the _PS0 method restores the duty cycle of 0% the GPU driver set on suspend and then the GPU driver first updates just the enabled bit in the pwm_state from 0 to 1, causing us to write the same values again, before restoring the pre-suspend duty-cycle in a separate pwm_apply call. When writing the update bit the second time, without changing any of the values the update bit clears immediately / instantly, instead of staying 1 for a while as usual. After this the next setting of the update bit seems to be ignored, causing the restoring of the pre-suspend duty-cycle to not get applied. This makes the backlight come up with a 0% dutycycle after suspend/resume. Any further brightness changes after this do work. This commit moves the setting of the update bit into pwm_lpss_prepare() and only sets the bit if we have actually changed any of the values. This avoids the setting of the update bit the second time we configure the PWM to 0% dutycycle, this fixes the backlight coming up with 0% duty-cycle after a suspend/resume. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
281 lines
7.3 KiB
C
281 lines
7.3 KiB
C
/*
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* Intel Low Power Subsystem PWM controller driver
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*
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* Copyright (C) 2014, Intel Corporation
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* Author: Mika Westerberg <mika.westerberg@linux.intel.com>
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* Author: Chew Kean Ho <kean.ho.chew@intel.com>
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* Author: Chang Rebecca Swee Fun <rebecca.swee.fun.chang@intel.com>
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* Author: Chew Chiau Ee <chiau.ee.chew@intel.com>
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* Author: Alan Cox <alan@linux.intel.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <linux/iopoll.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/pm_runtime.h>
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#include <linux/time.h>
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#include "pwm-lpss.h"
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#define PWM 0x00000000
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#define PWM_ENABLE BIT(31)
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#define PWM_SW_UPDATE BIT(30)
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#define PWM_BASE_UNIT_SHIFT 8
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#define PWM_ON_TIME_DIV_MASK 0x000000ff
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/* Size of each PWM register space if multiple */
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#define PWM_SIZE 0x400
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static inline struct pwm_lpss_chip *to_lpwm(struct pwm_chip *chip)
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{
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return container_of(chip, struct pwm_lpss_chip, chip);
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}
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static inline u32 pwm_lpss_read(const struct pwm_device *pwm)
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{
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struct pwm_lpss_chip *lpwm = to_lpwm(pwm->chip);
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return readl(lpwm->regs + pwm->hwpwm * PWM_SIZE + PWM);
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}
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static inline void pwm_lpss_write(const struct pwm_device *pwm, u32 value)
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{
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struct pwm_lpss_chip *lpwm = to_lpwm(pwm->chip);
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writel(value, lpwm->regs + pwm->hwpwm * PWM_SIZE + PWM);
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}
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static int pwm_lpss_wait_for_update(struct pwm_device *pwm)
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{
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struct pwm_lpss_chip *lpwm = to_lpwm(pwm->chip);
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const void __iomem *addr = lpwm->regs + pwm->hwpwm * PWM_SIZE + PWM;
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const unsigned int ms = 500 * USEC_PER_MSEC;
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u32 val;
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int err;
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/*
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* PWM Configuration register has SW_UPDATE bit that is set when a new
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* configuration is written to the register. The bit is automatically
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* cleared at the start of the next output cycle by the IP block.
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*
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* If one writes a new configuration to the register while it still has
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* the bit enabled, PWM may freeze. That is, while one can still write
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* to the register, it won't have an effect. Thus, we try to sleep long
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* enough that the bit gets cleared and make sure the bit is not
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* enabled while we update the configuration.
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*/
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err = readl_poll_timeout(addr, val, !(val & PWM_SW_UPDATE), 40, ms);
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if (err)
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dev_err(pwm->chip->dev, "PWM_SW_UPDATE was not cleared\n");
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return err;
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}
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static inline int pwm_lpss_is_updating(struct pwm_device *pwm)
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{
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return (pwm_lpss_read(pwm) & PWM_SW_UPDATE) ? -EBUSY : 0;
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}
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static void pwm_lpss_prepare(struct pwm_lpss_chip *lpwm, struct pwm_device *pwm,
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int duty_ns, int period_ns)
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{
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unsigned long long on_time_div;
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unsigned long c = lpwm->info->clk_rate, base_unit_range;
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unsigned long long base_unit, freq = NSEC_PER_SEC;
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u32 orig_ctrl, ctrl;
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do_div(freq, period_ns);
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/*
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* The equation is:
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* base_unit = round(base_unit_range * freq / c)
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*/
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base_unit_range = BIT(lpwm->info->base_unit_bits) - 1;
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freq *= base_unit_range;
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base_unit = DIV_ROUND_CLOSEST_ULL(freq, c);
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on_time_div = 255ULL * duty_ns;
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do_div(on_time_div, period_ns);
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on_time_div = 255ULL - on_time_div;
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orig_ctrl = ctrl = pwm_lpss_read(pwm);
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ctrl &= ~PWM_ON_TIME_DIV_MASK;
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ctrl &= ~(base_unit_range << PWM_BASE_UNIT_SHIFT);
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base_unit &= base_unit_range;
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ctrl |= (u32) base_unit << PWM_BASE_UNIT_SHIFT;
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ctrl |= on_time_div;
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if (orig_ctrl != ctrl) {
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pwm_lpss_write(pwm, ctrl);
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pwm_lpss_write(pwm, ctrl | PWM_SW_UPDATE);
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}
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}
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static inline void pwm_lpss_cond_enable(struct pwm_device *pwm, bool cond)
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{
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if (cond)
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pwm_lpss_write(pwm, pwm_lpss_read(pwm) | PWM_ENABLE);
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}
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static int pwm_lpss_apply(struct pwm_chip *chip, struct pwm_device *pwm,
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struct pwm_state *state)
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{
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struct pwm_lpss_chip *lpwm = to_lpwm(chip);
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int ret;
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if (state->enabled) {
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if (!pwm_is_enabled(pwm)) {
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pm_runtime_get_sync(chip->dev);
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ret = pwm_lpss_is_updating(pwm);
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if (ret) {
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pm_runtime_put(chip->dev);
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return ret;
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}
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pwm_lpss_prepare(lpwm, pwm, state->duty_cycle, state->period);
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pwm_lpss_cond_enable(pwm, lpwm->info->bypass == false);
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ret = pwm_lpss_wait_for_update(pwm);
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if (ret) {
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pm_runtime_put(chip->dev);
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return ret;
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}
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pwm_lpss_cond_enable(pwm, lpwm->info->bypass == true);
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} else {
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ret = pwm_lpss_is_updating(pwm);
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if (ret)
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return ret;
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pwm_lpss_prepare(lpwm, pwm, state->duty_cycle, state->period);
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return pwm_lpss_wait_for_update(pwm);
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}
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} else if (pwm_is_enabled(pwm)) {
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pwm_lpss_write(pwm, pwm_lpss_read(pwm) & ~PWM_ENABLE);
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pm_runtime_put(chip->dev);
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}
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return 0;
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}
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/* This function gets called once from pwmchip_add to get the initial state */
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static void pwm_lpss_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
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struct pwm_state *state)
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{
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struct pwm_lpss_chip *lpwm = to_lpwm(chip);
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unsigned long base_unit_range;
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unsigned long long base_unit, freq, on_time_div;
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u32 ctrl;
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base_unit_range = BIT(lpwm->info->base_unit_bits);
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ctrl = pwm_lpss_read(pwm);
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on_time_div = 255 - (ctrl & PWM_ON_TIME_DIV_MASK);
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base_unit = (ctrl >> PWM_BASE_UNIT_SHIFT) & (base_unit_range - 1);
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freq = base_unit * lpwm->info->clk_rate;
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do_div(freq, base_unit_range);
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if (freq == 0)
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state->period = NSEC_PER_SEC;
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else
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state->period = NSEC_PER_SEC / (unsigned long)freq;
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on_time_div *= state->period;
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do_div(on_time_div, 255);
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state->duty_cycle = on_time_div;
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state->polarity = PWM_POLARITY_NORMAL;
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state->enabled = !!(ctrl & PWM_ENABLE);
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if (state->enabled)
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pm_runtime_get(chip->dev);
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}
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static const struct pwm_ops pwm_lpss_ops = {
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.apply = pwm_lpss_apply,
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.get_state = pwm_lpss_get_state,
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.owner = THIS_MODULE,
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};
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struct pwm_lpss_chip *pwm_lpss_probe(struct device *dev, struct resource *r,
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const struct pwm_lpss_boardinfo *info)
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{
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struct pwm_lpss_chip *lpwm;
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unsigned long c;
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int ret;
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if (WARN_ON(info->npwm > MAX_PWMS))
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return ERR_PTR(-ENODEV);
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lpwm = devm_kzalloc(dev, sizeof(*lpwm), GFP_KERNEL);
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if (!lpwm)
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return ERR_PTR(-ENOMEM);
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lpwm->regs = devm_ioremap_resource(dev, r);
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if (IS_ERR(lpwm->regs))
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return ERR_CAST(lpwm->regs);
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lpwm->info = info;
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c = lpwm->info->clk_rate;
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if (!c)
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return ERR_PTR(-EINVAL);
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lpwm->chip.dev = dev;
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lpwm->chip.ops = &pwm_lpss_ops;
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lpwm->chip.base = -1;
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lpwm->chip.npwm = info->npwm;
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ret = pwmchip_add(&lpwm->chip);
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if (ret) {
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dev_err(dev, "failed to add PWM chip: %d\n", ret);
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return ERR_PTR(ret);
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}
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return lpwm;
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}
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EXPORT_SYMBOL_GPL(pwm_lpss_probe);
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int pwm_lpss_remove(struct pwm_lpss_chip *lpwm)
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{
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int i;
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for (i = 0; i < lpwm->info->npwm; i++) {
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if (pwm_is_enabled(&lpwm->chip.pwms[i]))
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pm_runtime_put(lpwm->chip.dev);
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}
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return pwmchip_remove(&lpwm->chip);
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}
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EXPORT_SYMBOL_GPL(pwm_lpss_remove);
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int pwm_lpss_suspend(struct device *dev)
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{
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struct pwm_lpss_chip *lpwm = dev_get_drvdata(dev);
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int i;
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for (i = 0; i < lpwm->info->npwm; i++)
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lpwm->saved_ctrl[i] = readl(lpwm->regs + i * PWM_SIZE + PWM);
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return 0;
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}
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EXPORT_SYMBOL_GPL(pwm_lpss_suspend);
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int pwm_lpss_resume(struct device *dev)
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{
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struct pwm_lpss_chip *lpwm = dev_get_drvdata(dev);
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int i;
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for (i = 0; i < lpwm->info->npwm; i++)
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writel(lpwm->saved_ctrl[i], lpwm->regs + i * PWM_SIZE + PWM);
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return 0;
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}
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EXPORT_SYMBOL_GPL(pwm_lpss_resume);
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MODULE_DESCRIPTION("PWM driver for Intel LPSS");
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MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
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MODULE_LICENSE("GPL v2");
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