forked from luck/tmp_suning_uos_patched
c001899a5d
Use unified assembler syntax (UAL) in headers. Divided syntax is considered deprecated. This will also allow to build the kernel using LLVM's integrated assembler. Signed-off-by: Stefan Agner <stefan@agner.ch> Acked-by: Nicolas Pitre <nico@linaro.org> Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
108 lines
2.1 KiB
C
108 lines
2.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#include <asm/assembler.h>
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#include <asm/unwind.h>
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#if __LINUX_ARM_ARCH__ >= 6
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.macro bitop, name, instr
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ENTRY( \name )
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UNWIND( .fnstart )
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ands ip, r1, #3
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strbne r1, [ip] @ assert word-aligned
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mov r2, #1
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and r3, r0, #31 @ Get bit offset
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mov r0, r0, lsr #5
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add r1, r1, r0, lsl #2 @ Get word offset
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#if __LINUX_ARM_ARCH__ >= 7 && defined(CONFIG_SMP)
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.arch_extension mp
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ALT_SMP(W(pldw) [r1])
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ALT_UP(W(nop))
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#endif
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mov r3, r2, lsl r3
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1: ldrex r2, [r1]
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\instr r2, r2, r3
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strex r0, r2, [r1]
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cmp r0, #0
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bne 1b
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bx lr
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UNWIND( .fnend )
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ENDPROC(\name )
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.endm
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.macro testop, name, instr, store
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ENTRY( \name )
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UNWIND( .fnstart )
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ands ip, r1, #3
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strbne r1, [ip] @ assert word-aligned
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mov r2, #1
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and r3, r0, #31 @ Get bit offset
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mov r0, r0, lsr #5
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add r1, r1, r0, lsl #2 @ Get word offset
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mov r3, r2, lsl r3 @ create mask
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smp_dmb
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#if __LINUX_ARM_ARCH__ >= 7 && defined(CONFIG_SMP)
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.arch_extension mp
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ALT_SMP(W(pldw) [r1])
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ALT_UP(W(nop))
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#endif
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1: ldrex r2, [r1]
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ands r0, r2, r3 @ save old value of bit
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\instr r2, r2, r3 @ toggle bit
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strex ip, r2, [r1]
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cmp ip, #0
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bne 1b
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smp_dmb
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cmp r0, #0
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movne r0, #1
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2: bx lr
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UNWIND( .fnend )
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ENDPROC(\name )
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.endm
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#else
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.macro bitop, name, instr
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ENTRY( \name )
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UNWIND( .fnstart )
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ands ip, r1, #3
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strbne r1, [ip] @ assert word-aligned
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and r2, r0, #31
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mov r0, r0, lsr #5
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mov r3, #1
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mov r3, r3, lsl r2
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save_and_disable_irqs ip
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ldr r2, [r1, r0, lsl #2]
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\instr r2, r2, r3
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str r2, [r1, r0, lsl #2]
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restore_irqs ip
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ret lr
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UNWIND( .fnend )
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ENDPROC(\name )
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.endm
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/**
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* testop - implement a test_and_xxx_bit operation.
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* @instr: operational instruction
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* @store: store instruction
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*
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* Note: we can trivially conditionalise the store instruction
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* to avoid dirtying the data cache.
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*/
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.macro testop, name, instr, store
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ENTRY( \name )
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UNWIND( .fnstart )
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ands ip, r1, #3
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strbne r1, [ip] @ assert word-aligned
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and r3, r0, #31
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mov r0, r0, lsr #5
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save_and_disable_irqs ip
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ldr r2, [r1, r0, lsl #2]!
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mov r0, #1
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tst r2, r0, lsl r3
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\instr r2, r2, r0, lsl r3
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\store r2, [r1]
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moveq r0, #0
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restore_irqs ip
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ret lr
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UNWIND( .fnend )
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ENDPROC(\name )
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.endm
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#endif
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