forked from luck/tmp_suning_uos_patched
514604c6d1
pcibus_to_node provides a way for the Linux kernel to identify to which node a certain pcibus connects to. Allocations of control structures for devices can then be made on the node where the pci bus is located to allow local access during interrupt and other device manipulation. This patch provides a new "node" field in the the pci_controller structure. The node field will be set based on ACPI information (thanks to Alex Williamson <alex.williamson@hp.com for that piece). Signed-off-by: Christoph Lameter <clameter@sgi.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
129 lines
3.2 KiB
C
129 lines
3.2 KiB
C
/*
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* linux/include/asm-ia64/topology.h
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*
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* Copyright (C) 2002, Erich Focht, NEC
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*
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* All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#ifndef _ASM_IA64_TOPOLOGY_H
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#define _ASM_IA64_TOPOLOGY_H
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#include <asm/acpi.h>
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#include <asm/numa.h>
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#include <asm/smp.h>
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#ifdef CONFIG_NUMA
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/*
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* Returns the number of the node containing CPU 'cpu'
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*/
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#define cpu_to_node(cpu) (int)(cpu_to_node_map[cpu])
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/*
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* Returns a bitmask of CPUs on Node 'node'.
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*/
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#define node_to_cpumask(node) (node_to_cpu_mask[node])
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/*
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* Returns the number of the node containing Node 'nid'.
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* Not implemented here. Multi-level hierarchies detected with
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* the help of node_distance().
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*/
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#define parent_node(nid) (nid)
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/*
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* Returns the number of the first CPU on Node 'node'.
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*/
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#define node_to_first_cpu(node) (__ffs(node_to_cpumask(node)))
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/*
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* Determines the node for a given pci bus
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*/
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#define pcibus_to_node(bus) PCI_CONTROLLER(bus)->node
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void build_cpu_to_node_map(void);
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#define SD_CPU_INIT (struct sched_domain) { \
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.span = CPU_MASK_NONE, \
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.parent = NULL, \
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.groups = NULL, \
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.min_interval = 1, \
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.max_interval = 4, \
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.busy_factor = 64, \
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.imbalance_pct = 125, \
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.cache_hot_time = (10*1000000), \
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.per_cpu_gain = 100, \
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.cache_nice_tries = 2, \
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.busy_idx = 2, \
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.idle_idx = 1, \
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.newidle_idx = 2, \
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.wake_idx = 1, \
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.forkexec_idx = 1, \
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.flags = SD_LOAD_BALANCE \
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| SD_BALANCE_NEWIDLE \
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| SD_BALANCE_EXEC \
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| SD_WAKE_AFFINE, \
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.last_balance = jiffies, \
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.balance_interval = 1, \
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.nr_balance_failed = 0, \
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}
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/* sched_domains SD_NODE_INIT for IA64 NUMA machines */
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#define SD_NODE_INIT (struct sched_domain) { \
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.span = CPU_MASK_NONE, \
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.parent = NULL, \
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.groups = NULL, \
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.min_interval = 8, \
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.max_interval = 8*(min(num_online_cpus(), 32)), \
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.busy_factor = 64, \
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.imbalance_pct = 125, \
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.cache_hot_time = (10*1000000), \
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.cache_nice_tries = 2, \
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.busy_idx = 3, \
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.idle_idx = 2, \
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.newidle_idx = 0, /* unused */ \
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.wake_idx = 1, \
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.forkexec_idx = 1, \
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.per_cpu_gain = 100, \
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.flags = SD_LOAD_BALANCE \
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| SD_BALANCE_EXEC \
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| SD_BALANCE_FORK \
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| SD_WAKE_BALANCE, \
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.last_balance = jiffies, \
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.balance_interval = 64, \
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.nr_balance_failed = 0, \
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}
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/* sched_domains SD_ALLNODES_INIT for IA64 NUMA machines */
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#define SD_ALLNODES_INIT (struct sched_domain) { \
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.span = CPU_MASK_NONE, \
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.parent = NULL, \
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.groups = NULL, \
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.min_interval = 64, \
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.max_interval = 64*num_online_cpus(), \
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.busy_factor = 128, \
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.imbalance_pct = 133, \
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.cache_hot_time = (10*1000000), \
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.cache_nice_tries = 1, \
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.busy_idx = 3, \
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.idle_idx = 3, \
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.newidle_idx = 0, /* unused */ \
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.wake_idx = 0, /* unused */ \
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.forkexec_idx = 0, /* unused */ \
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.per_cpu_gain = 100, \
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.flags = SD_LOAD_BALANCE, \
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.last_balance = jiffies, \
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.balance_interval = 64, \
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.nr_balance_failed = 0, \
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}
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#endif /* CONFIG_NUMA */
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#include <asm-generic/topology.h>
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#endif /* _ASM_IA64_TOPOLOGY_H */
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