forked from luck/tmp_suning_uos_patched
5dae15b21d
Synopsys DesignWare core based PCIe controllers in Tegra 194 SoC interface with Universal PHY (UPHY) module through a PIPE2UPHY (P2U) module. For each PCIe lane of a controller, there is a P2U unit instantiated at hardware level. This driver provides support for the programming required for each P2U that is going to be used for a PCIe controller. Signed-off-by: Vidya Sagar <vidyas@nvidia.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Kishon Vijay Abraham I <kishon@ti.com> Acked-by: Thierry Reding <treding@nvidia.com> |
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| .. | ||
| Kconfig | ||
| Makefile | ||
| phy-tegra194-p2u.c | ||
| xusb-tegra124.c | ||
| xusb-tegra186.c | ||
| xusb-tegra210.c | ||
| xusb.c | ||
| xusb.h | ||