forked from luck/tmp_suning_uos_patched
cbaa118ecf
Presently most of the 29-bit physical parts do P1/P2 segmentation with a 1:1 cached/uncached mapping, jumping between the two to control the caching behaviour. This provides the basic infrastructure to maintain this behaviour on 32-bit physical parts that don't map P1/P2 at all, using a shiny new linker section and corresponding fixmap entry. Signed-off-by: Stuart Menefy <stuart.menefy@st.com> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
100 lines
2.5 KiB
C
100 lines
2.5 KiB
C
#ifndef __ASM_SH_SYSTEM_32_H
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#define __ASM_SH_SYSTEM_32_H
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#include <linux/types.h>
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struct task_struct *__switch_to(struct task_struct *prev,
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struct task_struct *next);
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/*
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* switch_to() should switch tasks to task nr n, first
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*/
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#define switch_to(prev, next, last) \
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do { \
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register u32 *__ts1 __asm__ ("r1") = &prev->thread.sp; \
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register u32 *__ts2 __asm__ ("r2") = &prev->thread.pc; \
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register u32 *__ts4 __asm__ ("r4") = (u32 *)prev; \
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register u32 *__ts5 __asm__ ("r5") = (u32 *)next; \
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register u32 *__ts6 __asm__ ("r6") = &next->thread.sp; \
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register u32 __ts7 __asm__ ("r7") = next->thread.pc; \
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struct task_struct *__last; \
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\
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__asm__ __volatile__ ( \
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".balign 4\n\t" \
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"stc.l gbr, @-r15\n\t" \
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"sts.l pr, @-r15\n\t" \
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"mov.l r8, @-r15\n\t" \
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"mov.l r9, @-r15\n\t" \
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"mov.l r10, @-r15\n\t" \
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"mov.l r11, @-r15\n\t" \
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"mov.l r12, @-r15\n\t" \
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"mov.l r13, @-r15\n\t" \
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"mov.l r14, @-r15\n\t" \
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"mov.l r15, @r1\t! save SP\n\t" \
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"mov.l @r6, r15\t! change to new stack\n\t" \
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"mova 1f, %0\n\t" \
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"mov.l %0, @r2\t! save PC\n\t" \
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"mov.l 2f, %0\n\t" \
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"jmp @%0\t! call __switch_to\n\t" \
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" lds r7, pr\t! with return to new PC\n\t" \
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".balign 4\n" \
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"2:\n\t" \
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".long __switch_to\n" \
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"1:\n\t" \
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"mov.l @r15+, r14\n\t" \
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"mov.l @r15+, r13\n\t" \
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"mov.l @r15+, r12\n\t" \
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"mov.l @r15+, r11\n\t" \
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"mov.l @r15+, r10\n\t" \
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"mov.l @r15+, r9\n\t" \
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"mov.l @r15+, r8\n\t" \
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"lds.l @r15+, pr\n\t" \
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"ldc.l @r15+, gbr\n\t" \
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: "=z" (__last) \
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: "r" (__ts1), "r" (__ts2), "r" (__ts4), \
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"r" (__ts5), "r" (__ts6), "r" (__ts7) \
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: "r3", "t"); \
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\
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last = __last; \
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} while (0)
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#define __uses_jump_to_uncached __attribute__ ((__section__ (".uncached.text")))
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/*
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* Jump to uncached area.
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* When handling TLB or caches, we need to do it from an uncached area.
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*/
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#define jump_to_uncached() \
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do { \
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unsigned long __dummy; \
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\
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__asm__ __volatile__( \
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"mova 1f, %0\n\t" \
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"add %1, %0\n\t" \
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"jmp @%0\n\t" \
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" nop\n\t" \
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".balign 4\n" \
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"1:" \
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: "=&z" (__dummy) \
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: "r" (cached_to_uncached)); \
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} while (0)
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/*
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* Back to cached area.
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*/
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#define back_to_cached() \
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do { \
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unsigned long __dummy; \
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ctrl_barrier(); \
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__asm__ __volatile__( \
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"mov.l 1f, %0\n\t" \
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"jmp @%0\n\t" \
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" nop\n\t" \
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".balign 4\n" \
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"1: .long 2f\n" \
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"2:" \
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: "=&r" (__dummy)); \
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} while (0)
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#endif /* __ASM_SH_SYSTEM_32_H */
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