forked from luck/tmp_suning_uos_patched
7034228792
Having received another series of whitespace patches I decided to do this once and for all rather than dealing with this kind of patches trickling in forever. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
406 lines
9.1 KiB
C
406 lines
9.1 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
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*/
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/slab.h>
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#include <linux/delay.h>
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#include <linux/i2c.h>
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#include <linux/platform_device.h>
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#define PIC32_I2CxCON 0x0000
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#define PIC32_I2CCON_ON (1<<15)
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#define PIC32_I2CCON_ACKDT (1<<5)
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#define PIC32_I2CCON_ACKEN (1<<4)
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#define PIC32_I2CCON_RCEN (1<<3)
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#define PIC32_I2CCON_PEN (1<<2)
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#define PIC32_I2CCON_RSEN (1<<1)
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#define PIC32_I2CCON_SEN (1<<0)
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#define PIC32_I2CxCONCLR 0x0004
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#define PIC32_I2CxCONSET 0x0008
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#define PIC32_I2CxSTAT 0x0010
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#define PIC32_I2CxSTATCLR 0x0014
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#define PIC32_I2CSTAT_ACKSTAT (1<<15)
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#define PIC32_I2CSTAT_TRSTAT (1<<14)
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#define PIC32_I2CSTAT_BCL (1<<10)
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#define PIC32_I2CSTAT_IWCOL (1<<7)
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#define PIC32_I2CSTAT_I2COV (1<<6)
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#define PIC32_I2CxBRG 0x0040
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#define PIC32_I2CxTRN 0x0050
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#define PIC32_I2CxRCV 0x0060
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static DEFINE_SPINLOCK(pic32_bus_lock);
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static void __iomem *bus_xfer = (void __iomem *)0xbf000600;
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static void __iomem *bus_status = (void __iomem *)0xbf000060;
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#define DELAY() udelay(100)
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static inline unsigned int ioready(void)
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{
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return readl(bus_status) & 1;
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}
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static inline void wait_ioready(void)
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{
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do { } while (!ioready());
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}
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static inline void wait_ioclear(void)
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{
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do { } while (ioready());
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}
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static inline void check_ioclear(void)
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{
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if (ioready()) {
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do {
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(void) readl(bus_xfer);
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DELAY();
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} while (ioready());
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}
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}
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static u32 pic32_bus_readl(u32 reg)
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{
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unsigned long flags;
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u32 status, val;
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spin_lock_irqsave(&pic32_bus_lock, flags);
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check_ioclear();
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writel((0x01 << 24) | (reg & 0x00ffffff), bus_xfer);
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DELAY();
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wait_ioready();
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status = readl(bus_xfer);
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DELAY();
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val = readl(bus_xfer);
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wait_ioclear();
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spin_unlock_irqrestore(&pic32_bus_lock, flags);
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return val;
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}
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static void pic32_bus_writel(u32 val, u32 reg)
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{
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unsigned long flags;
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u32 status;
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spin_lock_irqsave(&pic32_bus_lock, flags);
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check_ioclear();
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writel((0x10 << 24) | (reg & 0x00ffffff), bus_xfer);
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DELAY();
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writel(val, bus_xfer);
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DELAY();
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wait_ioready();
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status = readl(bus_xfer);
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wait_ioclear();
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spin_unlock_irqrestore(&pic32_bus_lock, flags);
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}
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struct pic32_i2c_platform_data {
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u32 base;
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struct i2c_adapter adap;
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u32 xfer_timeout;
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u32 ack_timeout;
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u32 ctl_timeout;
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};
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static inline void pic32_i2c_start(struct pic32_i2c_platform_data *adap)
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{
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pic32_bus_writel(PIC32_I2CCON_SEN, adap->base + PIC32_I2CxCONSET);
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}
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static inline void pic32_i2c_stop(struct pic32_i2c_platform_data *adap)
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{
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pic32_bus_writel(PIC32_I2CCON_PEN, adap->base + PIC32_I2CxCONSET);
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}
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static inline void pic32_i2c_ack(struct pic32_i2c_platform_data *adap)
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{
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pic32_bus_writel(PIC32_I2CCON_ACKDT, adap->base + PIC32_I2CxCONCLR);
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pic32_bus_writel(PIC32_I2CCON_ACKEN, adap->base + PIC32_I2CxCONSET);
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}
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static inline void pic32_i2c_nack(struct pic32_i2c_platform_data *adap)
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{
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pic32_bus_writel(PIC32_I2CCON_ACKDT, adap->base + PIC32_I2CxCONSET);
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pic32_bus_writel(PIC32_I2CCON_ACKEN, adap->base + PIC32_I2CxCONSET);
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}
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static inline int pic32_i2c_idle(struct pic32_i2c_platform_data *adap)
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{
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int i;
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for (i = 0; i < adap->ctl_timeout; i++) {
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if (((pic32_bus_readl(adap->base + PIC32_I2CxCON) &
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(PIC32_I2CCON_ACKEN | PIC32_I2CCON_RCEN |
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PIC32_I2CCON_PEN | PIC32_I2CCON_RSEN |
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PIC32_I2CCON_SEN)) == 0) &&
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((pic32_bus_readl(adap->base + PIC32_I2CxSTAT) &
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(PIC32_I2CSTAT_TRSTAT)) == 0))
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return 0;
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udelay(1);
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}
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return -ETIMEDOUT;
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}
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static inline u32 pic32_i2c_master_write(struct pic32_i2c_platform_data *adap,
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u32 byte)
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{
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pic32_bus_writel(byte, adap->base + PIC32_I2CxTRN);
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return pic32_bus_readl(adap->base + PIC32_I2CxSTAT) &
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PIC32_I2CSTAT_IWCOL;
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}
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static inline u32 pic32_i2c_master_read(struct pic32_i2c_platform_data *adap)
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{
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pic32_bus_writel(PIC32_I2CCON_RCEN, adap->base + PIC32_I2CxCONSET);
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while (pic32_bus_readl(adap->base + PIC32_I2CxCON) & PIC32_I2CCON_RCEN)
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;
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pic32_bus_writel(PIC32_I2CSTAT_I2COV, adap->base + PIC32_I2CxSTATCLR);
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return pic32_bus_readl(adap->base + PIC32_I2CxRCV);
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}
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static int pic32_i2c_address(struct pic32_i2c_platform_data *adap,
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unsigned int addr, int rd)
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{
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pic32_i2c_idle(adap);
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pic32_i2c_start(adap);
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pic32_i2c_idle(adap);
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addr <<= 1;
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if (rd)
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addr |= 1;
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if (pic32_i2c_master_write(adap, addr))
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return -EIO;
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pic32_i2c_idle(adap);
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if (pic32_bus_readl(adap->base + PIC32_I2CxSTAT) &
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PIC32_I2CSTAT_ACKSTAT)
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return -EIO;
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return 0;
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}
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static int sead3_i2c_read(struct pic32_i2c_platform_data *adap,
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unsigned char *buf, unsigned int len)
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{
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u32 data;
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int i;
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i = 0;
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while (i < len) {
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data = pic32_i2c_master_read(adap);
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buf[i++] = data;
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if (i < len)
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pic32_i2c_ack(adap);
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else
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pic32_i2c_nack(adap);
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}
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pic32_i2c_stop(adap);
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pic32_i2c_idle(adap);
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return 0;
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}
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static int sead3_i2c_write(struct pic32_i2c_platform_data *adap,
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unsigned char *buf, unsigned int len)
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{
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int i;
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u32 data;
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i = 0;
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while (i < len) {
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data = buf[i];
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if (pic32_i2c_master_write(adap, data))
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return -EIO;
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pic32_i2c_idle(adap);
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if (pic32_bus_readl(adap->base + PIC32_I2CxSTAT) &
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PIC32_I2CSTAT_ACKSTAT)
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return -EIO;
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i++;
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}
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pic32_i2c_stop(adap);
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pic32_i2c_idle(adap);
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return 0;
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}
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static int sead3_pic32_platform_xfer(struct i2c_adapter *i2c_adap,
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struct i2c_msg *msgs, int num)
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{
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struct pic32_i2c_platform_data *adap = i2c_adap->algo_data;
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struct i2c_msg *p;
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int i, err = 0;
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for (i = 0; i < num; i++) {
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#define __BUFSIZE 80
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int ii;
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static char buf[__BUFSIZE];
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char *b = buf;
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p = &msgs[i];
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b += sprintf(buf, " [%d bytes]", p->len);
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if ((p->flags & I2C_M_RD) == 0) {
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for (ii = 0; ii < p->len; ii++) {
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if (b < &buf[__BUFSIZE-4]) {
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b += sprintf(b, " %02x", p->buf[ii]);
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} else {
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strcat(b, "...");
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break;
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}
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}
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}
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}
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for (i = 0; !err && i < num; i++) {
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p = &msgs[i];
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err = pic32_i2c_address(adap, p->addr, p->flags & I2C_M_RD);
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if (err || !p->len)
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continue;
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if (p->flags & I2C_M_RD)
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err = sead3_i2c_read(adap, p->buf, p->len);
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else
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err = sead3_i2c_write(adap, p->buf, p->len);
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}
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/* Return the number of messages processed, or the error code. */
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if (err == 0)
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err = num;
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return err;
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}
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static u32 sead3_pic32_platform_func(struct i2c_adapter *adap)
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{
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return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
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}
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static const struct i2c_algorithm sead3_platform_algo = {
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.master_xfer = sead3_pic32_platform_xfer,
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.functionality = sead3_pic32_platform_func,
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};
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static void sead3_i2c_platform_setup(struct pic32_i2c_platform_data *priv)
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{
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pic32_bus_writel(500, priv->base + PIC32_I2CxBRG);
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pic32_bus_writel(PIC32_I2CCON_ON, priv->base + PIC32_I2CxCONCLR);
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pic32_bus_writel(PIC32_I2CCON_ON, priv->base + PIC32_I2CxCONSET);
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pic32_bus_writel(PIC32_I2CSTAT_BCL | PIC32_I2CSTAT_IWCOL,
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priv->base + PIC32_I2CxSTATCLR);
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}
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static int sead3_i2c_platform_probe(struct platform_device *pdev)
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{
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struct pic32_i2c_platform_data *priv;
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struct resource *r;
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int ret;
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r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (!r) {
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ret = -ENODEV;
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goto out;
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}
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priv = kzalloc(sizeof(struct pic32_i2c_platform_data), GFP_KERNEL);
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if (!priv) {
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ret = -ENOMEM;
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goto out;
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}
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priv->base = r->start;
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if (!priv->base) {
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ret = -EBUSY;
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goto out_mem;
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}
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priv->xfer_timeout = 200;
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priv->ack_timeout = 200;
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priv->ctl_timeout = 200;
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priv->adap.nr = pdev->id;
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priv->adap.algo = &sead3_platform_algo;
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priv->adap.algo_data = priv;
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priv->adap.dev.parent = &pdev->dev;
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strlcpy(priv->adap.name, "SEAD3 PIC32", sizeof(priv->adap.name));
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sead3_i2c_platform_setup(priv);
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ret = i2c_add_numbered_adapter(&priv->adap);
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if (ret == 0) {
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platform_set_drvdata(pdev, priv);
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return 0;
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}
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out_mem:
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kfree(priv);
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out:
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return ret;
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}
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static int sead3_i2c_platform_remove(struct platform_device *pdev)
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{
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struct pic32_i2c_platform_data *priv = platform_get_drvdata(pdev);
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platform_set_drvdata(pdev, NULL);
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i2c_del_adapter(&priv->adap);
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kfree(priv);
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return 0;
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}
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#ifdef CONFIG_PM
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static int sead3_i2c_platform_suspend(struct platform_device *pdev,
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pm_message_t state)
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{
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dev_dbg(&pdev->dev, "i2c_platform_disable\n");
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return 0;
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}
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static int sead3_i2c_platform_resume(struct platform_device *pdev)
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{
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struct pic32_i2c_platform_data *priv = platform_get_drvdata(pdev);
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dev_dbg(&pdev->dev, "sead3_i2c_platform_setup\n");
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sead3_i2c_platform_setup(priv);
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return 0;
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}
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#else
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#define sead3_i2c_platform_suspend NULL
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#define sead3_i2c_platform_resume NULL
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#endif
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static struct platform_driver sead3_i2c_platform_driver = {
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.driver = {
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.name = "sead3-i2c",
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.owner = THIS_MODULE,
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},
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.probe = sead3_i2c_platform_probe,
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.remove = sead3_i2c_platform_remove,
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.suspend = sead3_i2c_platform_suspend,
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.resume = sead3_i2c_platform_resume,
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};
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static int __init sead3_i2c_platform_init(void)
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{
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return platform_driver_register(&sead3_i2c_platform_driver);
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}
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module_init(sead3_i2c_platform_init);
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static void __exit sead3_i2c_platform_exit(void)
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{
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platform_driver_unregister(&sead3_i2c_platform_driver);
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}
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module_exit(sead3_i2c_platform_exit);
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MODULE_AUTHOR("Chris Dearman, MIPS Technologies INC.");
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MODULE_DESCRIPTION("SEAD3 PIC32 I2C driver");
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MODULE_LICENSE("GPL");
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