forked from luck/tmp_suning_uos_patched
8ff374b9c2
Replace hardcoded CP0 PRId and CP1 FPIR register access masks throughout. The change does not touch places that use shifted or partial masks. Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5838/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
118 lines
2.5 KiB
C
118 lines
2.5 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
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*/
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#include <linux/init.h>
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#include <asm/cpu.h>
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#include <asm/setup.h>
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#include <asm/time.h>
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#include <asm/irq.h>
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#include <asm/mips-boards/generic.h>
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unsigned long cpu_khz;
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static int mips_cpu_timer_irq;
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static int mips_cpu_perf_irq;
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static void mips_timer_dispatch(void)
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{
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do_IRQ(mips_cpu_timer_irq);
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}
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static void mips_perf_dispatch(void)
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{
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do_IRQ(mips_cpu_perf_irq);
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}
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static void __iomem *status_reg = (void __iomem *)0xbf000410;
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/*
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* Estimate CPU frequency. Sets mips_hpt_frequency as a side-effect.
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*/
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static unsigned int __init estimate_cpu_frequency(void)
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{
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unsigned int prid = read_c0_prid() & (PRID_COMP_MASK | PRID_IMP_MASK);
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unsigned int tick = 0;
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unsigned int freq;
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unsigned int orig;
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unsigned long flags;
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local_irq_save(flags);
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orig = readl(status_reg) & 0x2; /* get original sample */
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/* wait for transition */
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while ((readl(status_reg) & 0x2) == orig)
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;
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orig = orig ^ 0x2; /* flip the bit */
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write_c0_count(0);
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/* wait 1 second (the sampling clock transitions every 10ms) */
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while (tick < 100) {
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/* wait for transition */
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while ((readl(status_reg) & 0x2) == orig)
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;
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orig = orig ^ 0x2; /* flip the bit */
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tick++;
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}
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freq = read_c0_count();
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local_irq_restore(flags);
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mips_hpt_frequency = freq;
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/* Adjust for processor */
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if ((prid != (PRID_COMP_MIPS | PRID_IMP_20KC)) &&
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(prid != (PRID_COMP_MIPS | PRID_IMP_25KF)))
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freq *= 2;
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freq += 5000; /* rounding */
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freq -= freq%10000;
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return freq ;
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}
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void read_persistent_clock(struct timespec *ts)
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{
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ts->tv_sec = 0;
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ts->tv_nsec = 0;
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}
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static void __init plat_perf_setup(void)
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{
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if (cp0_perfcount_irq >= 0) {
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if (cpu_has_vint)
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set_vi_handler(cp0_perfcount_irq, mips_perf_dispatch);
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mips_cpu_perf_irq = MIPS_CPU_IRQ_BASE + cp0_perfcount_irq;
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}
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}
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unsigned int get_c0_compare_int(void)
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{
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if (cpu_has_vint)
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set_vi_handler(cp0_compare_irq, mips_timer_dispatch);
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mips_cpu_timer_irq = MIPS_CPU_IRQ_BASE + cp0_compare_irq;
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return mips_cpu_timer_irq;
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}
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void __init plat_time_init(void)
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{
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unsigned int est_freq;
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est_freq = estimate_cpu_frequency();
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pr_debug("CPU frequency %d.%02d MHz\n", (est_freq / 1000000),
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(est_freq % 1000000) * 100 / 1000000);
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cpu_khz = est_freq / 1000;
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mips_scroll_message();
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plat_perf_setup();
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}
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