forked from luck/tmp_suning_uos_patched
484889fc85
The resume() implementation octeon_switch.S examines the saved cp0_status register. We were clobbering the entire pt_regs structure in kernel threads leading to random crashes. When switching away from a kernel thread, the saved cp0_status is examined and if bit 30 is set it is cleared and the CP2 state saved into the pt_regs structure. Since the kernel thread stack overlaid the pt_regs structure this resulted in a corrupt stack. When the kthread with the corrupt stack was resumed, it could crash if it used any of the data in the stack that was clobbered. We fix it by moving the kernel thread stack down so it doesn't overlay pt_regs. Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
232 lines
5.9 KiB
ArmAsm
232 lines
5.9 KiB
ArmAsm
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 1994, 1995 Waldorf Electronics
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* Written by Ralf Baechle and Andreas Busse
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* Copyright (C) 1994 - 99, 2003, 06 Ralf Baechle
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* Copyright (C) 1996 Paul M. Antoine
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* Modified for DECStation and hence R3000 support by Paul M. Antoine
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* Further modifications by David S. Miller and Harald Koerfgen
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* Copyright (C) 1999 Silicon Graphics, Inc.
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* Kevin Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
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* Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
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*/
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#include <linux/init.h>
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#include <linux/threads.h>
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#include <asm/addrspace.h>
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#include <asm/asm.h>
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#include <asm/asmmacro.h>
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#include <asm/irqflags.h>
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#include <asm/regdef.h>
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#include <asm/page.h>
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#include <asm/pgtable-bits.h>
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#include <asm/mipsregs.h>
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#include <asm/stackframe.h>
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#include <kernel-entry-init.h>
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/*
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* inputs are the text nasid in t1, data nasid in t2.
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*/
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.macro MAPPED_KERNEL_SETUP_TLB
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#ifdef CONFIG_MAPPED_KERNEL
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/*
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* This needs to read the nasid - assume 0 for now.
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* Drop in 0xffffffffc0000000 in tlbhi, 0+VG in tlblo_0,
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* 0+DVG in tlblo_1.
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*/
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dli t0, 0xffffffffc0000000
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dmtc0 t0, CP0_ENTRYHI
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li t0, 0x1c000 # Offset of text into node memory
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dsll t1, NASID_SHFT # Shift text nasid into place
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dsll t2, NASID_SHFT # Same for data nasid
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or t1, t1, t0 # Physical load address of kernel text
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or t2, t2, t0 # Physical load address of kernel data
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dsrl t1, 12 # 4K pfn
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dsrl t2, 12 # 4K pfn
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dsll t1, 6 # Get pfn into place
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dsll t2, 6 # Get pfn into place
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li t0, ((_PAGE_GLOBAL|_PAGE_VALID| _CACHE_CACHABLE_COW) >> 6)
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or t0, t0, t1
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mtc0 t0, CP0_ENTRYLO0 # physaddr, VG, cach exlwr
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li t0, ((_PAGE_GLOBAL|_PAGE_VALID| _PAGE_DIRTY|_CACHE_CACHABLE_COW) >> 6)
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or t0, t0, t2
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mtc0 t0, CP0_ENTRYLO1 # physaddr, DVG, cach exlwr
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li t0, 0x1ffe000 # MAPPED_KERN_TLBMASK, TLBPGMASK_16M
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mtc0 t0, CP0_PAGEMASK
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li t0, 0 # KMAP_INX
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mtc0 t0, CP0_INDEX
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li t0, 1
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mtc0 t0, CP0_WIRED
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tlbwi
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#else
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mtc0 zero, CP0_WIRED
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#endif
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.endm
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/*
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* For the moment disable interrupts, mark the kernel mode and
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* set ST0_KX so that the CPU does not spit fire when using
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* 64-bit addresses. A full initialization of the CPU's status
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* register is done later in per_cpu_trap_init().
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*/
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.macro setup_c0_status set clr
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.set push
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#ifdef CONFIG_MIPS_MT_SMTC
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/*
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* For SMTC, we need to set privilege and disable interrupts only for
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* the current TC, using the TCStatus register.
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*/
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mfc0 t0, CP0_TCSTATUS
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/* Fortunately CU 0 is in the same place in both registers */
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/* Set TCU0, TMX, TKSU (for later inversion) and IXMT */
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li t1, ST0_CU0 | 0x08001c00
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or t0, t1
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/* Clear TKSU, leave IXMT */
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xori t0, 0x00001800
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mtc0 t0, CP0_TCSTATUS
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_ehb
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/* We need to leave the global IE bit set, but clear EXL...*/
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mfc0 t0, CP0_STATUS
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or t0, ST0_CU0 | ST0_EXL | ST0_ERL | \set | \clr
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xor t0, ST0_EXL | ST0_ERL | \clr
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mtc0 t0, CP0_STATUS
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#else
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mfc0 t0, CP0_STATUS
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or t0, ST0_CU0|\set|0x1f|\clr
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xor t0, 0x1f|\clr
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mtc0 t0, CP0_STATUS
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.set noreorder
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sll zero,3 # ehb
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#endif
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.set pop
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.endm
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.macro setup_c0_status_pri
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#ifdef CONFIG_64BIT
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setup_c0_status ST0_KX 0
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#else
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setup_c0_status 0 0
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#endif
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.endm
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.macro setup_c0_status_sec
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#ifdef CONFIG_64BIT
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setup_c0_status ST0_KX ST0_BEV
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#else
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setup_c0_status 0 ST0_BEV
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#endif
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.endm
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#ifndef CONFIG_NO_EXCEPT_FILL
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/*
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* Reserved space for exception handlers.
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* Necessary for machines which link their kernels at KSEG0.
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*/
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.fill 0x400
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#endif
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EXPORT(_stext)
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#ifdef CONFIG_BOOT_RAW
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/*
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* Give us a fighting chance of running if execution beings at the
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* kernel load address. This is needed because this platform does
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* not have a ELF loader yet.
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*/
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FEXPORT(__kernel_entry)
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j kernel_entry
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#endif
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__REF
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NESTED(kernel_entry, 16, sp) # kernel entry point
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kernel_entry_setup # cpu specific setup
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setup_c0_status_pri
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/* We might not get launched at the address the kernel is linked to,
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so we jump there. */
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PTR_LA t0, 0f
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jr t0
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0:
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#ifdef CONFIG_MIPS_MT_SMTC
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/*
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* In SMTC kernel, "CLI" is thread-specific, in TCStatus.
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* We still need to enable interrupts globally in Status,
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* and clear EXL/ERL.
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*
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* TCContext is used to track interrupt levels under
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* service in SMTC kernel. Clear for boot TC before
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* allowing any interrupts.
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*/
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mtc0 zero, CP0_TCCONTEXT
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mfc0 t0, CP0_STATUS
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ori t0, t0, 0xff1f
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xori t0, t0, 0x001e
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mtc0 t0, CP0_STATUS
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#endif /* CONFIG_MIPS_MT_SMTC */
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PTR_LA t0, __bss_start # clear .bss
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LONG_S zero, (t0)
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PTR_LA t1, __bss_stop - LONGSIZE
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1:
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PTR_ADDIU t0, LONGSIZE
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LONG_S zero, (t0)
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bne t0, t1, 1b
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LONG_S a0, fw_arg0 # firmware arguments
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LONG_S a1, fw_arg1
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LONG_S a2, fw_arg2
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LONG_S a3, fw_arg3
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MTC0 zero, CP0_CONTEXT # clear context register
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PTR_LA $28, init_thread_union
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/* Set the SP after an empty pt_regs. */
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PTR_LI sp, _THREAD_SIZE - 32 - PT_SIZE
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PTR_ADDU sp, $28
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set_saved_sp sp, t0, t1
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PTR_SUBU sp, 4 * SZREG # init stack pointer
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j start_kernel
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END(kernel_entry)
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__CPUINIT
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#ifdef CONFIG_SMP
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/*
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* SMP slave cpus entry point. Board specific code for bootstrap calls this
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* function after setting up the stack and gp registers.
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*/
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NESTED(smp_bootstrap, 16, sp)
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#ifdef CONFIG_MIPS_MT_SMTC
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/*
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* Read-modify-writes of Status must be atomic, and this
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* is one case where CLI is invoked without EXL being
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* necessarily set. The CLI and setup_c0_status will
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* in fact be redundant for all but the first TC of
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* each VPE being booted.
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*/
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DMT 10 # dmt t2 /* t0, t1 are used by CLI and setup_c0_status() */
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jal mips_ihb
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#endif /* CONFIG_MIPS_MT_SMTC */
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setup_c0_status_sec
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smp_slave_setup
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#ifdef CONFIG_MIPS_MT_SMTC
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andi t2, t2, VPECONTROL_TE
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beqz t2, 2f
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EMT # emt
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2:
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#endif /* CONFIG_MIPS_MT_SMTC */
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j start_secondary
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END(smp_bootstrap)
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#endif /* CONFIG_SMP */
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__FINIT
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