Sylwester Nawrocki a701fe3851 clk: exynos4: Add CLK_GET_RATE_NOCACHE flag for the Exynos4x12 ISP clocks ... The ISP clock registers belong to the ISP power domain and may change their values if this power domain is switched off/on. Add CLK_GET_RATE_NOCACHE flags to ensure we do not rely on invalid cached data when setting or getting frequency of those clocks. Without this fix the FIMC-IS Cortex-A5 core and AXI bus clocks have incorrect frequencies, which breaks the ISP operation and starting the video pipeline fails with timeouts reported by the FIMC-IS firmware. See related commit 722a860ecb "[media] exynos4-is: Fix FIMC-IS clocks initialization" for more details. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>		2013-08-13 10:01:56 -07:00
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mmp
mvebu
mxs
rockchip
samsung
socfpga
spear
sunxi
tegra
ux500
versatile
x86
zynq
clk-axi-clkgen.c
clk-bcm2835.c
clk-composite.c
clk-devres.c
clk-divider.c
clk-fixed-factor.c
clk-fixed-rate.c
clk-gate.c
clk-highbank.c
clk-ls1x.c
clk-max77686.c
clk-mux.c
clk-nomadik.c
clk-nspire.c
clk-ppc-corenet.c
clk-prima2.c
clk-si5351.c
clk-si5351.h
clk-twl6040.c
clk-u300.c
clk-vt8500.c
clk-wm831x.c
clk.c
clkdev.c
Kconfig
Makefile