forked from luck/tmp_suning_uos_patched
0cd61b68c3
Untested, but this should fix up the bulk of the totally mechanical issues, and should make the actual detail fixing easier. Signed-off-by: Linus Torvalds <torvalds@osdl.org>
585 lines
14 KiB
C
585 lines
14 KiB
C
/*
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* linux/arch/arm/mach-realview/core.c
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*
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* Copyright (C) 1999 - 2003 ARM Limited
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* Copyright (C) 2000 Deep Blue Solutions Ltd
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <linux/init.h>
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#include <linux/platform_device.h>
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#include <linux/dma-mapping.h>
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#include <linux/sysdev.h>
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#include <linux/interrupt.h>
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#include <linux/amba/bus.h>
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#include <linux/amba/clcd.h>
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#include <asm/system.h>
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#include <asm/hardware.h>
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#include <asm/io.h>
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#include <asm/irq.h>
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#include <asm/leds.h>
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#include <asm/hardware/arm_timer.h>
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#include <asm/hardware/icst307.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/flash.h>
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#include <asm/mach/irq.h>
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#include <asm/mach/time.h>
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#include <asm/mach/map.h>
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#include <asm/mach/mmc.h>
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#include <asm/hardware/gic.h>
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#include "core.h"
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#include "clock.h"
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#define REALVIEW_REFCOUNTER (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_24MHz_OFFSET)
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/*
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* This is the RealView sched_clock implementation. This has
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* a resolution of 41.7ns, and a maximum value of about 179s.
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*/
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unsigned long long sched_clock(void)
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{
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unsigned long long v;
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v = (unsigned long long)readl(REALVIEW_REFCOUNTER) * 125;
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do_div(v, 3);
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return v;
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}
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#define REALVIEW_FLASHCTRL (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_FLASH_OFFSET)
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static int realview_flash_init(void)
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{
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u32 val;
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val = __raw_readl(REALVIEW_FLASHCTRL);
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val &= ~REALVIEW_FLASHPROG_FLVPPEN;
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__raw_writel(val, REALVIEW_FLASHCTRL);
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return 0;
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}
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static void realview_flash_exit(void)
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{
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u32 val;
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val = __raw_readl(REALVIEW_FLASHCTRL);
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val &= ~REALVIEW_FLASHPROG_FLVPPEN;
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__raw_writel(val, REALVIEW_FLASHCTRL);
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}
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static void realview_flash_set_vpp(int on)
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{
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u32 val;
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val = __raw_readl(REALVIEW_FLASHCTRL);
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if (on)
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val |= REALVIEW_FLASHPROG_FLVPPEN;
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else
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val &= ~REALVIEW_FLASHPROG_FLVPPEN;
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__raw_writel(val, REALVIEW_FLASHCTRL);
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}
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static struct flash_platform_data realview_flash_data = {
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.map_name = "cfi_probe",
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.width = 4,
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.init = realview_flash_init,
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.exit = realview_flash_exit,
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.set_vpp = realview_flash_set_vpp,
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};
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static struct resource realview_flash_resource = {
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.start = REALVIEW_FLASH_BASE,
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.end = REALVIEW_FLASH_BASE + REALVIEW_FLASH_SIZE,
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.flags = IORESOURCE_MEM,
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};
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struct platform_device realview_flash_device = {
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.name = "armflash",
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.id = 0,
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.dev = {
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.platform_data = &realview_flash_data,
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},
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.num_resources = 1,
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.resource = &realview_flash_resource,
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};
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static struct resource realview_smc91x_resources[] = {
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[0] = {
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.start = REALVIEW_ETH_BASE,
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.end = REALVIEW_ETH_BASE + SZ_64K - 1,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = IRQ_ETH,
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.end = IRQ_ETH,
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.flags = IORESOURCE_IRQ,
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},
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};
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struct platform_device realview_smc91x_device = {
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.name = "smc91x",
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.id = 0,
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.num_resources = ARRAY_SIZE(realview_smc91x_resources),
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.resource = realview_smc91x_resources,
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};
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#define REALVIEW_SYSMCI (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_MCI_OFFSET)
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static unsigned int realview_mmc_status(struct device *dev)
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{
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struct amba_device *adev = container_of(dev, struct amba_device, dev);
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u32 mask;
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if (adev->res.start == REALVIEW_MMCI0_BASE)
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mask = 1;
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else
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mask = 2;
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return readl(REALVIEW_SYSMCI) & mask;
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}
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struct mmc_platform_data realview_mmc0_plat_data = {
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.ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
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.status = realview_mmc_status,
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};
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struct mmc_platform_data realview_mmc1_plat_data = {
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.ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
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.status = realview_mmc_status,
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};
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/*
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* Clock handling
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*/
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static const struct icst307_params realview_oscvco_params = {
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.ref = 24000,
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.vco_max = 200000,
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.vd_min = 4 + 8,
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.vd_max = 511 + 8,
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.rd_min = 1 + 2,
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.rd_max = 127 + 2,
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};
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static void realview_oscvco_set(struct clk *clk, struct icst307_vco vco)
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{
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void __iomem *sys_lock = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_LOCK_OFFSET;
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void __iomem *sys_osc = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_OSC4_OFFSET;
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u32 val;
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val = readl(sys_osc) & ~0x7ffff;
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val |= vco.v | (vco.r << 9) | (vco.s << 16);
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writel(0xa05f, sys_lock);
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writel(val, sys_osc);
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writel(0, sys_lock);
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}
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struct clk realview_clcd_clk = {
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.name = "CLCDCLK",
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.params = &realview_oscvco_params,
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.setvco = realview_oscvco_set,
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};
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/*
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* CLCD support.
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*/
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#define SYS_CLCD_NLCDIOON (1 << 2)
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#define SYS_CLCD_VDDPOSSWITCH (1 << 3)
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#define SYS_CLCD_PWR3V5SWITCH (1 << 4)
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#define SYS_CLCD_ID_MASK (0x1f << 8)
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#define SYS_CLCD_ID_SANYO_3_8 (0x00 << 8)
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#define SYS_CLCD_ID_UNKNOWN_8_4 (0x01 << 8)
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#define SYS_CLCD_ID_EPSON_2_2 (0x02 << 8)
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#define SYS_CLCD_ID_SANYO_2_5 (0x07 << 8)
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#define SYS_CLCD_ID_VGA (0x1f << 8)
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static struct clcd_panel vga = {
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.mode = {
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.name = "VGA",
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.refresh = 60,
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.xres = 640,
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.yres = 480,
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.pixclock = 39721,
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.left_margin = 40,
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.right_margin = 24,
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.upper_margin = 32,
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.lower_margin = 11,
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.hsync_len = 96,
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.vsync_len = 2,
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.sync = 0,
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.vmode = FB_VMODE_NONINTERLACED,
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},
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.width = -1,
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.height = -1,
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.tim2 = TIM2_BCD | TIM2_IPC,
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.cntl = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
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.bpp = 16,
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};
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static struct clcd_panel sanyo_3_8_in = {
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.mode = {
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.name = "Sanyo QVGA",
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.refresh = 116,
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.xres = 320,
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.yres = 240,
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.pixclock = 100000,
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.left_margin = 6,
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.right_margin = 6,
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.upper_margin = 5,
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.lower_margin = 5,
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.hsync_len = 6,
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.vsync_len = 6,
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.sync = 0,
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.vmode = FB_VMODE_NONINTERLACED,
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},
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.width = -1,
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.height = -1,
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.tim2 = TIM2_BCD,
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.cntl = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
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.bpp = 16,
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};
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static struct clcd_panel sanyo_2_5_in = {
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.mode = {
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.name = "Sanyo QVGA Portrait",
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.refresh = 116,
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.xres = 240,
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.yres = 320,
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.pixclock = 100000,
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.left_margin = 20,
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.right_margin = 10,
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.upper_margin = 2,
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.lower_margin = 2,
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.hsync_len = 10,
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.vsync_len = 2,
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.sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
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.vmode = FB_VMODE_NONINTERLACED,
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},
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.width = -1,
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.height = -1,
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.tim2 = TIM2_IVS | TIM2_IHS | TIM2_IPC,
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.cntl = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
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.bpp = 16,
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};
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static struct clcd_panel epson_2_2_in = {
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.mode = {
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.name = "Epson QCIF",
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.refresh = 390,
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.xres = 176,
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.yres = 220,
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.pixclock = 62500,
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.left_margin = 3,
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.right_margin = 2,
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.upper_margin = 1,
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.lower_margin = 0,
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.hsync_len = 3,
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.vsync_len = 2,
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.sync = 0,
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.vmode = FB_VMODE_NONINTERLACED,
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},
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.width = -1,
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.height = -1,
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.tim2 = TIM2_BCD | TIM2_IPC,
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.cntl = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
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.bpp = 16,
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};
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/*
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* Detect which LCD panel is connected, and return the appropriate
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* clcd_panel structure. Note: we do not have any information on
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* the required timings for the 8.4in panel, so we presently assume
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* VGA timings.
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*/
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static struct clcd_panel *realview_clcd_panel(void)
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{
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void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET;
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struct clcd_panel *panel = &vga;
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u32 val;
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val = readl(sys_clcd) & SYS_CLCD_ID_MASK;
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if (val == SYS_CLCD_ID_SANYO_3_8)
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panel = &sanyo_3_8_in;
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else if (val == SYS_CLCD_ID_SANYO_2_5)
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panel = &sanyo_2_5_in;
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else if (val == SYS_CLCD_ID_EPSON_2_2)
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panel = &epson_2_2_in;
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else if (val == SYS_CLCD_ID_VGA)
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panel = &vga;
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else {
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printk(KERN_ERR "CLCD: unknown LCD panel ID 0x%08x, using VGA\n",
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val);
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panel = &vga;
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}
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return panel;
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}
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/*
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* Disable all display connectors on the interface module.
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*/
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static void realview_clcd_disable(struct clcd_fb *fb)
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{
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void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET;
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u32 val;
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val = readl(sys_clcd);
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val &= ~SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
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writel(val, sys_clcd);
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}
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/*
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* Enable the relevant connector on the interface module.
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*/
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static void realview_clcd_enable(struct clcd_fb *fb)
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{
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void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET;
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u32 val;
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/*
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* Enable the PSUs
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*/
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val = readl(sys_clcd);
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val |= SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
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writel(val, sys_clcd);
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}
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static unsigned long framesize = SZ_1M;
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static int realview_clcd_setup(struct clcd_fb *fb)
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{
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dma_addr_t dma;
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fb->panel = realview_clcd_panel();
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fb->fb.screen_base = dma_alloc_writecombine(&fb->dev->dev, framesize,
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&dma, GFP_KERNEL);
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if (!fb->fb.screen_base) {
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printk(KERN_ERR "CLCD: unable to map framebuffer\n");
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return -ENOMEM;
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}
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fb->fb.fix.smem_start = dma;
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fb->fb.fix.smem_len = framesize;
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return 0;
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}
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static int realview_clcd_mmap(struct clcd_fb *fb, struct vm_area_struct *vma)
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{
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return dma_mmap_writecombine(&fb->dev->dev, vma,
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fb->fb.screen_base,
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fb->fb.fix.smem_start,
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fb->fb.fix.smem_len);
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}
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static void realview_clcd_remove(struct clcd_fb *fb)
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{
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dma_free_writecombine(&fb->dev->dev, fb->fb.fix.smem_len,
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fb->fb.screen_base, fb->fb.fix.smem_start);
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}
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struct clcd_board clcd_plat_data = {
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.name = "RealView",
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.check = clcdfb_check,
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.decode = clcdfb_decode,
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.disable = realview_clcd_disable,
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.enable = realview_clcd_enable,
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.setup = realview_clcd_setup,
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.mmap = realview_clcd_mmap,
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.remove = realview_clcd_remove,
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};
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#ifdef CONFIG_LEDS
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#define VA_LEDS_BASE (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_LED_OFFSET)
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void realview_leds_event(led_event_t ledevt)
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{
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unsigned long flags;
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u32 val;
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local_irq_save(flags);
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val = readl(VA_LEDS_BASE);
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switch (ledevt) {
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case led_idle_start:
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val = val & ~REALVIEW_SYS_LED0;
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break;
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case led_idle_end:
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val = val | REALVIEW_SYS_LED0;
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break;
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case led_timer:
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val = val ^ REALVIEW_SYS_LED1;
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break;
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case led_halted:
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val = 0;
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break;
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default:
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break;
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}
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writel(val, VA_LEDS_BASE);
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local_irq_restore(flags);
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}
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#endif /* CONFIG_LEDS */
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/*
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* Where is the timer (VA)?
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*/
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#define TIMER0_VA_BASE __io_address(REALVIEW_TIMER0_1_BASE)
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#define TIMER1_VA_BASE (__io_address(REALVIEW_TIMER0_1_BASE) + 0x20)
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#define TIMER2_VA_BASE __io_address(REALVIEW_TIMER2_3_BASE)
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#define TIMER3_VA_BASE (__io_address(REALVIEW_TIMER2_3_BASE) + 0x20)
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/*
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* How long is the timer interval?
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*/
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#define TIMER_INTERVAL (TICKS_PER_uSEC * mSEC_10)
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#if TIMER_INTERVAL >= 0x100000
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#define TIMER_RELOAD (TIMER_INTERVAL >> 8)
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#define TIMER_DIVISOR (TIMER_CTRL_DIV256)
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#define TICKS2USECS(x) (256 * (x) / TICKS_PER_uSEC)
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#elif TIMER_INTERVAL >= 0x10000
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#define TIMER_RELOAD (TIMER_INTERVAL >> 4) /* Divide by 16 */
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#define TIMER_DIVISOR (TIMER_CTRL_DIV16)
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#define TICKS2USECS(x) (16 * (x) / TICKS_PER_uSEC)
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#else
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#define TIMER_RELOAD (TIMER_INTERVAL)
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#define TIMER_DIVISOR (TIMER_CTRL_DIV1)
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#define TICKS2USECS(x) ((x) / TICKS_PER_uSEC)
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#endif
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/*
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* Returns number of ms since last clock interrupt. Note that interrupts
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* will have been disabled by do_gettimeoffset()
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*/
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static unsigned long realview_gettimeoffset(void)
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{
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unsigned long ticks1, ticks2, status;
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/*
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* Get the current number of ticks. Note that there is a race
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* condition between us reading the timer and checking for
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* an interrupt. We get around this by ensuring that the
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* counter has not reloaded between our two reads.
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*/
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ticks2 = readl(TIMER0_VA_BASE + TIMER_VALUE) & 0xffff;
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do {
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ticks1 = ticks2;
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status = __raw_readl(__io_address(REALVIEW_GIC_DIST_BASE + GIC_DIST_PENDING_SET)
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+ ((IRQ_TIMERINT0_1 >> 5) << 2));
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ticks2 = readl(TIMER0_VA_BASE + TIMER_VALUE) & 0xffff;
|
|
} while (ticks2 > ticks1);
|
|
|
|
/*
|
|
* Number of ticks since last interrupt.
|
|
*/
|
|
ticks1 = TIMER_RELOAD - ticks2;
|
|
|
|
/*
|
|
* Interrupt pending? If so, we've reloaded once already.
|
|
*
|
|
* FIXME: Need to check this is effectively timer 0 that expires
|
|
*/
|
|
if (status & IRQMASK_TIMERINT0_1)
|
|
ticks1 += TIMER_RELOAD;
|
|
|
|
/*
|
|
* Convert the ticks to usecs
|
|
*/
|
|
return TICKS2USECS(ticks1);
|
|
}
|
|
|
|
/*
|
|
* IRQ handler for the timer
|
|
*/
|
|
static irqreturn_t realview_timer_interrupt(int irq, void *dev_id)
|
|
{
|
|
write_seqlock(&xtime_lock);
|
|
|
|
// ...clear the interrupt
|
|
writel(1, TIMER0_VA_BASE + TIMER_INTCLR);
|
|
|
|
timer_tick();
|
|
|
|
#if defined(CONFIG_SMP) && !defined(CONFIG_LOCAL_TIMERS)
|
|
smp_send_timer();
|
|
update_process_times(user_mode(get_irq_regs()));
|
|
#endif
|
|
|
|
write_sequnlock(&xtime_lock);
|
|
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
static struct irqaction realview_timer_irq = {
|
|
.name = "RealView Timer Tick",
|
|
.flags = IRQF_DISABLED | IRQF_TIMER,
|
|
.handler = realview_timer_interrupt,
|
|
};
|
|
|
|
/*
|
|
* Set up timer interrupt, and return the current time in seconds.
|
|
*/
|
|
static void __init realview_timer_init(void)
|
|
{
|
|
u32 val;
|
|
|
|
/*
|
|
* set clock frequency:
|
|
* REALVIEW_REFCLK is 32KHz
|
|
* REALVIEW_TIMCLK is 1MHz
|
|
*/
|
|
val = readl(__io_address(REALVIEW_SCTL_BASE));
|
|
writel((REALVIEW_TIMCLK << REALVIEW_TIMER1_EnSel) |
|
|
(REALVIEW_TIMCLK << REALVIEW_TIMER2_EnSel) |
|
|
(REALVIEW_TIMCLK << REALVIEW_TIMER3_EnSel) |
|
|
(REALVIEW_TIMCLK << REALVIEW_TIMER4_EnSel) | val,
|
|
__io_address(REALVIEW_SCTL_BASE));
|
|
|
|
/*
|
|
* Initialise to a known state (all timers off)
|
|
*/
|
|
writel(0, TIMER0_VA_BASE + TIMER_CTRL);
|
|
writel(0, TIMER1_VA_BASE + TIMER_CTRL);
|
|
writel(0, TIMER2_VA_BASE + TIMER_CTRL);
|
|
writel(0, TIMER3_VA_BASE + TIMER_CTRL);
|
|
|
|
writel(TIMER_RELOAD, TIMER0_VA_BASE + TIMER_LOAD);
|
|
writel(TIMER_RELOAD, TIMER0_VA_BASE + TIMER_VALUE);
|
|
writel(TIMER_DIVISOR | TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC |
|
|
TIMER_CTRL_IE, TIMER0_VA_BASE + TIMER_CTRL);
|
|
|
|
/*
|
|
* Make irqs happen for the system timer
|
|
*/
|
|
setup_irq(IRQ_TIMERINT0_1, &realview_timer_irq);
|
|
}
|
|
|
|
struct sys_timer realview_timer = {
|
|
.init = realview_timer_init,
|
|
.offset = realview_gettimeoffset,
|
|
};
|