forked from luck/tmp_suning_uos_patched
568d135d33
Pull MIPS updates from Ralf Baechle: "Boston platform support: - Document DT bindings - Add CLK driver for board clocks CM: - Avoid per-core locking with CM3 & higher - WARN on attempt to lock invalid VP, not BUG CPS: - Select CONFIG_SYS_SUPPORTS_SCHED_SMT for MIPSr6 - Prevent multi-core with dcache aliasing - Handle cores not powering down more gracefully - Handle spurious VP starts more gracefully DSP: - Add lwx & lhx missaligned access support eBPF: - Add MIPS support along with many supporting change to add the required infrastructure Generic arch code: - Misc sysmips MIPS_ATOMIC_SET fixes - Drop duplicate HAVE_SYSCALL_TRACEPOINTS - Negate error syscall return in trace - Correct forced syscall errors - Traced negative syscalls should return -ENOSYS - Allow samples/bpf/tracex5 to access syscall arguments for sane traces - Cleanup from old Kconfig options in defconfigs - Fix PREF instruction usage by memcpy for MIPS R6 - Fix various special cases in the FPU eulation - Fix some special cases in MIPS16e2 support - Fix MIPS I ISA /proc/cpuinfo reporting - Sort MIPS Kconfig alphabetically - Fix minimum alignment requirement of IRQ stack as required by ABI / GCC - Fix special cases in the module loader - Perform post-DMA cache flushes on systems with MAARs - Probe the I6500 CPU - Cleanup cmpxchg and add support for 1 and 2 byte operations - Use queued read/write locks (qrwlock) - Use queued spinlocks (qspinlock) - Add CPU shared FTLB feature detection - Handle tlbex-tlbp race condition - Allow storing pgd in C0_CONTEXT for MIPSr6 - Use current_cpu_type() in m4kc_tlbp_war() - Support Boston in the generic kernel Generic platform: - yamon-dt: Pull YAMON DT shim code out of SEAD-3 board - yamon-dt: Support > 256MB of RAM - yamon-dt: Use serial* rather than uart* aliases - Abstract FDT fixup application - Set RTC_ALWAYS_BCD to 0 - Add a MAINTAINERS entry core kernel: - qspinlock.c: include linux/prefetch.h Loongson 3: - Add support Perf: - Add I6500 support SEAD-3: - Remove GIC timer from DT - Set interrupt-parent per-device, not at root node - Fix GIC interrupt specifiers SMP: - Skip IPI setup if we only have a single CPU VDSO: - Make comment match reality - Improvements to time code in VDSO" * 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (86 commits) locking/qspinlock: Include linux/prefetch.h MIPS: Fix MIPS I ISA /proc/cpuinfo reporting MIPS: Fix minimum alignment requirement of IRQ stack MIPS: generic: Support MIPS Boston development boards MIPS: DTS: img: Don't attempt to build-in all .dtb files clk: boston: Add a driver for MIPS Boston board clocks dt-bindings: Document img,boston-clock binding MIPS: Traced negative syscalls should return -ENOSYS MIPS: Correct forced syscall errors MIPS: Negate error syscall return in trace MIPS: Drop duplicate HAVE_SYSCALL_TRACEPOINTS select MIPS16e2: Provide feature overrides for non-MIPS16 systems MIPS: MIPS16e2: Report ASE presence in /proc/cpuinfo MIPS: MIPS16e2: Subdecode extended LWSP/SWSP instructions MIPS: MIPS16e2: Identify ASE presence MIPS: VDSO: Fix a mismatch between comment and preprocessor constant MIPS: VDSO: Add implementation of gettimeofday() fallback MIPS: VDSO: Add implementation of clock_gettime() fallback MIPS: VDSO: Fix conversions in do_monotonic()/do_monotonic_coarse() MIPS: Use current_cpu_type() in m4kc_tlbp_war() ...
221 lines
4.6 KiB
C
221 lines
4.6 KiB
C
/*
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* Copyright (C) 2016 Imagination Technologies
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* Author: Paul Burton <paul.burton@imgtec.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/clocksource.h>
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#include <linux/init.h>
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#include <linux/irqchip.h>
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#include <linux/of_fdt.h>
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#include <linux/of_platform.h>
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#include <asm/fw/fw.h>
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#include <asm/irq_cpu.h>
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#include <asm/machine.h>
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#include <asm/mips-cpc.h>
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#include <asm/prom.h>
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#include <asm/smp-ops.h>
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#include <asm/time.h>
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static __initdata const void *fdt;
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static __initdata const struct mips_machine *mach;
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static __initdata const void *mach_match_data;
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void __init prom_init(void)
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{
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plat_get_fdt();
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BUG_ON(!fdt);
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}
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void __init *plat_get_fdt(void)
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{
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const struct mips_machine *check_mach;
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const struct of_device_id *match;
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if (fdt)
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/* Already set up */
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return (void *)fdt;
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if ((fw_arg0 == -2) && !fdt_check_header((void *)fw_arg1)) {
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/*
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* We booted using the UHI boot protocol, so we have been
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* provided with the appropriate device tree for the board.
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* Make use of it & search for any machine struct based upon
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* the root compatible string.
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*/
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fdt = (void *)fw_arg1;
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for_each_mips_machine(check_mach) {
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match = mips_machine_is_compatible(check_mach, fdt);
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if (match) {
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mach = check_mach;
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mach_match_data = match->data;
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break;
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}
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}
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} else if (IS_ENABLED(CONFIG_LEGACY_BOARDS)) {
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/*
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* We weren't booted using the UHI boot protocol, but do
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* support some number of boards with legacy boot protocols.
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* Attempt to find the right one.
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*/
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for_each_mips_machine(check_mach) {
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if (!check_mach->detect)
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continue;
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if (!check_mach->detect())
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continue;
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mach = check_mach;
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}
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/*
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* If we don't recognise the machine then we can't continue, so
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* die here.
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*/
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BUG_ON(!mach);
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/* Retrieve the machine's FDT */
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fdt = mach->fdt;
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}
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return (void *)fdt;
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}
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void __init plat_fdt_relocated(void *new_location)
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{
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/*
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* reset fdt as the cached value would point to the location
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* before relocations happened and update the location argument
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* if it was passed using UHI
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*/
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fdt = NULL;
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if (fw_arg0 == -2)
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fw_arg1 = (unsigned long)new_location;
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}
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void __init plat_mem_setup(void)
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{
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if (mach && mach->fixup_fdt)
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fdt = mach->fixup_fdt(fdt, mach_match_data);
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strlcpy(arcs_cmdline, boot_command_line, COMMAND_LINE_SIZE);
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__dt_setup_arch((void *)fdt);
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}
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void __init device_tree_init(void)
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{
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int err;
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unflatten_and_copy_device_tree();
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mips_cpc_probe();
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err = register_cps_smp_ops();
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if (err)
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err = register_up_smp_ops();
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}
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int __init apply_mips_fdt_fixups(void *fdt_out, size_t fdt_out_size,
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const void *fdt_in,
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const struct mips_fdt_fixup *fixups)
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{
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int err;
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err = fdt_open_into(fdt_in, fdt_out, fdt_out_size);
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if (err) {
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pr_err("Failed to open FDT\n");
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return err;
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}
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for (; fixups->apply; fixups++) {
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err = fixups->apply(fdt_out);
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if (err) {
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pr_err("Failed to apply FDT fixup \"%s\"\n",
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fixups->description);
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return err;
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}
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}
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err = fdt_pack(fdt_out);
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if (err)
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pr_err("Failed to pack FDT\n");
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return err;
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}
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void __init plat_time_init(void)
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{
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struct device_node *np;
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struct clk *clk;
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of_clk_init(NULL);
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if (!cpu_has_counter) {
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mips_hpt_frequency = 0;
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} else if (mach && mach->measure_hpt_freq) {
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mips_hpt_frequency = mach->measure_hpt_freq();
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} else {
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np = of_get_cpu_node(0, NULL);
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if (!np) {
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pr_err("Failed to get CPU node\n");
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return;
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}
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clk = of_clk_get(np, 0);
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if (IS_ERR(clk)) {
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pr_err("Failed to get CPU clock: %ld\n", PTR_ERR(clk));
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return;
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}
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mips_hpt_frequency = clk_get_rate(clk);
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clk_put(clk);
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switch (boot_cpu_type()) {
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case CPU_20KC:
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case CPU_25KF:
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/* The counter runs at the CPU clock rate */
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break;
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default:
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/* The counter runs at half the CPU clock rate */
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mips_hpt_frequency /= 2;
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break;
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}
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}
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timer_probe();
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}
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void __init arch_init_irq(void)
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{
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struct device_node *intc_node;
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intc_node = of_find_compatible_node(NULL, NULL,
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"mti,cpu-interrupt-controller");
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if (!cpu_has_veic && !intc_node)
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mips_cpu_irq_init();
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irqchip_init();
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}
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static int __init publish_devices(void)
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{
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if (!of_have_populated_dt())
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panic("Device-tree not present");
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if (of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL))
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panic("Failed to populate DT");
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return 0;
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}
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arch_initcall(publish_devices);
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void __init prom_free_prom_memory(void)
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{
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}
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