forked from luck/tmp_suning_uos_patched
9161d303af
On RUMI platform STIs are not enabled by default, contrary to the GIC spec. The bits for STIs in the enable/enable clear registers are also RW instead of RO. STIs need to be enabled at initialization time. Signed-off-by: Steve Muckle <smuckle@codeaurora.org> Signed-off-by: Daniel Walker <dwalker@codeaurora.org>
79 lines
2.1 KiB
C
79 lines
2.1 KiB
C
/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
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* 02110-1301, USA.
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*
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*/
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#include <linux/kernel.h>
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#include <linux/platform_device.h>
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#include <linux/io.h>
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#include <linux/irq.h>
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#include <asm/mach-types.h>
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#include <asm/mach/arch.h>
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#include <asm/hardware/gic.h>
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#include <mach/board.h>
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#include <mach/msm_iomap.h>
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void __iomem *gic_cpu_base_addr;
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unsigned long clk_get_max_axi_khz(void)
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{
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return 0;
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}
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static void __init msm8x60_map_io(void)
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{
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msm_map_msm8x60_io();
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}
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static void __init msm8x60_init_irq(void)
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{
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unsigned int i;
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gic_dist_init(0, MSM_QGIC_DIST_BASE, 1);
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gic_cpu_base_addr = (void *)MSM_QGIC_CPU_BASE;
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gic_cpu_init(0, MSM_QGIC_CPU_BASE);
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/* Edge trigger PPIs except AVS_SVICINT and AVS_SVICINTSWDONE */
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writel(0xFFFFD7FF, MSM_QGIC_DIST_BASE + GIC_DIST_CONFIG + 4);
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/* RUMI does not adhere to GIC spec by enabling STIs by default.
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* Enable/clear is supposed to be RO for STIs, but is RW on RUMI.
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*/
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writel(0x0000FFFF, MSM_QGIC_DIST_BASE + GIC_DIST_ENABLE_SET);
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/* FIXME: Not installing AVS_SVICINT and AVS_SVICINTSWDONE yet
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* as they are configured as level, which does not play nice with
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* handle_percpu_irq.
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*/
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for (i = GIC_PPI_START; i < GIC_SPI_START; i++) {
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if (i != AVS_SVICINT && i != AVS_SVICINTSWDONE)
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set_irq_handler(i, handle_percpu_irq);
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}
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}
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static void __init msm8x60_init(void)
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{
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}
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MACHINE_START(MSM8X60_RUMI3, "QCT MSM8X60 RUMI3")
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.map_io = msm8x60_map_io,
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.init_irq = msm8x60_init_irq,
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.init_machine = msm8x60_init,
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.timer = &msm_timer,
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MACHINE_END
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