forked from luck/tmp_suning_uos_patched
23fbee9dd5
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
160 lines
4.0 KiB
C
160 lines
4.0 KiB
C
/*
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* linux/arch/mips/tx4938/toshiba_rbtx4938/spi_txx9.c
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* Copyright (C) 2000-2001 Toshiba Corporation
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*
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* 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
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* terms of the GNU General Public License version 2. This program is
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* licensed "as is" without any warranty of any kind, whether express
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* or implied.
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*
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* Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
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*/
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#include <linux/init.h>
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#include <linux/delay.h>
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#include <linux/errno.h>
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#include <linux/interrupt.h>
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#include <linux/module.h>
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#include <linux/sched.h>
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#include <linux/spinlock.h>
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#include <linux/wait.h>
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#include <asm/tx4938/spi.h>
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#include <asm/tx4938/tx4938.h>
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static int (*txx9_spi_cs_func)(int chipid, int on);
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static DEFINE_SPINLOCK(txx9_spi_lock);
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extern unsigned int txx9_gbus_clock;
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#define SPI_FIFO_SIZE 4
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void __init txx9_spi_init(unsigned long base, int (*cs_func)(int chipid, int on))
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{
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txx9_spi_cs_func = cs_func;
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/* enter config mode */
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tx4938_spiptr->mcr = TXx9_SPMCR_CONFIG | TXx9_SPMCR_BCLR;
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}
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static DECLARE_WAIT_QUEUE_HEAD(txx9_spi_wait);
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static void txx9_spi_interrupt(int irq, void *dev_id, struct pt_regs *regs)
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{
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/* disable rx intr */
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tx4938_spiptr->cr0 &= ~TXx9_SPCR0_RBSIE;
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wake_up(&txx9_spi_wait);
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}
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static struct irqaction txx9_spi_action = {
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txx9_spi_interrupt, 0, 0, "spi", NULL, NULL,
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};
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void __init txx9_spi_irqinit(int irc_irq)
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{
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setup_irq(irc_irq, &txx9_spi_action);
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}
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int txx9_spi_io(int chipid, struct spi_dev_desc *desc,
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unsigned char **inbufs, unsigned int *incounts,
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unsigned char **outbufs, unsigned int *outcounts,
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int cansleep)
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{
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unsigned int incount, outcount;
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unsigned char *inp, *outp;
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int ret;
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unsigned long flags;
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spin_lock_irqsave(&txx9_spi_lock, flags);
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if ((tx4938_spiptr->mcr & TXx9_SPMCR_OPMODE) == TXx9_SPMCR_ACTIVE) {
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spin_unlock_irqrestore(&txx9_spi_lock, flags);
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return -EBUSY;
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}
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/* enter config mode */
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tx4938_spiptr->mcr = TXx9_SPMCR_CONFIG | TXx9_SPMCR_BCLR;
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tx4938_spiptr->cr0 =
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(desc->byteorder ? TXx9_SPCR0_SBOS : 0) |
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(desc->polarity ? TXx9_SPCR0_SPOL : 0) |
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(desc->phase ? TXx9_SPCR0_SPHA : 0) |
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0x08;
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tx4938_spiptr->cr1 =
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(((TXX9_IMCLK + desc->baud) / (2 * desc->baud) - 1) << 8) |
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0x08 /* 8 bit only */;
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/* enter active mode */
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tx4938_spiptr->mcr = TXx9_SPMCR_ACTIVE;
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spin_unlock_irqrestore(&txx9_spi_lock, flags);
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/* CS ON */
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if ((ret = txx9_spi_cs_func(chipid, 1)) < 0) {
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spin_unlock_irqrestore(&txx9_spi_lock, flags);
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return ret;
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}
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udelay(desc->tcss);
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/* do scatter IO */
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inp = inbufs ? *inbufs : NULL;
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outp = outbufs ? *outbufs : NULL;
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incount = 0;
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outcount = 0;
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while (1) {
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unsigned char data;
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unsigned int count;
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int i;
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if (!incount) {
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incount = incounts ? *incounts++ : 0;
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inp = (incount && inbufs) ? *inbufs++ : NULL;
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}
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if (!outcount) {
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outcount = outcounts ? *outcounts++ : 0;
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outp = (outcount && outbufs) ? *outbufs++ : NULL;
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}
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if (!inp && !outp)
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break;
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count = SPI_FIFO_SIZE;
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if (incount)
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count = min(count, incount);
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if (outcount)
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count = min(count, outcount);
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/* now tx must be idle... */
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while (!(tx4938_spiptr->sr & TXx9_SPSR_SIDLE))
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;
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tx4938_spiptr->cr0 =
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(tx4938_spiptr->cr0 & ~TXx9_SPCR0_RXIFL_MASK) |
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((count - 1) << 12);
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if (cansleep) {
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/* enable rx intr */
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tx4938_spiptr->cr0 |= TXx9_SPCR0_RBSIE;
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}
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/* send */
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for (i = 0; i < count; i++)
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tx4938_spiptr->dr = inp ? *inp++ : 0;
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/* wait all rx data */
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if (cansleep) {
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wait_event(txx9_spi_wait,
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tx4938_spiptr->sr & TXx9_SPSR_SRRDY);
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} else {
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while (!(tx4938_spiptr->sr & TXx9_SPSR_RBSI))
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;
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}
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/* receive */
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for (i = 0; i < count; i++) {
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data = tx4938_spiptr->dr;
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if (outp)
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*outp++ = data;
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}
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if (incount)
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incount -= count;
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if (outcount)
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outcount -= count;
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}
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/* CS OFF */
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udelay(desc->tcsh);
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txx9_spi_cs_func(chipid, 0);
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udelay(desc->tcsr);
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spin_lock_irqsave(&txx9_spi_lock, flags);
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/* enter config mode */
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tx4938_spiptr->mcr = TXx9_SPMCR_CONFIG | TXx9_SPMCR_BCLR;
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spin_unlock_irqrestore(&txx9_spi_lock, flags);
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return 0;
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}
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