forked from luck/tmp_suning_uos_patched
352c417ddb
Add support for 1G versions of Chelsio devices. Signed-off-by: Stephen Hemminger <shemminger@osdl.org> Signed-off-by: Jeff Garzik <jeff@garzik.org>
173 lines
6.0 KiB
C
173 lines
6.0 KiB
C
/* $Date: 2005/11/23 16:28:53 $ $RCSfile: vsc8244_reg.h,v $ $Revision: 1.1 $ */
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#ifndef CHELSIO_MV8E1XXX_H
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#define CHELSIO_MV8E1XXX_H
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#ifndef BMCR_SPEED1000
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# define BMCR_SPEED1000 0x40
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#endif
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#ifndef ADVERTISE_PAUSE
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# define ADVERTISE_PAUSE 0x400
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#endif
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#ifndef ADVERTISE_PAUSE_ASYM
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# define ADVERTISE_PAUSE_ASYM 0x800
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#endif
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/* Gigabit MII registers */
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#define MII_GBMR 1 /* 1000Base-T mode register */
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#define MII_GBCR 9 /* 1000Base-T control register */
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#define MII_GBSR 10 /* 1000Base-T status register */
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/* 1000Base-T control register fields */
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#define GBCR_ADV_1000HALF 0x100
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#define GBCR_ADV_1000FULL 0x200
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#define GBCR_PREFER_MASTER 0x400
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#define GBCR_MANUAL_AS_MASTER 0x800
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#define GBCR_MANUAL_CONFIG_ENABLE 0x1000
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/* 1000Base-T status register fields */
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#define GBSR_LP_1000HALF 0x400
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#define GBSR_LP_1000FULL 0x800
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#define GBSR_REMOTE_OK 0x1000
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#define GBSR_LOCAL_OK 0x2000
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#define GBSR_LOCAL_MASTER 0x4000
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#define GBSR_MASTER_FAULT 0x8000
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/* Vitesse PHY interrupt status bits. */
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#if 0
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#define VSC8244_INTR_JABBER 0x0001
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#define VSC8244_INTR_POLARITY_CHNG 0x0002
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#define VSC8244_INTR_ENG_DETECT_CHNG 0x0010
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#define VSC8244_INTR_DOWNSHIFT 0x0020
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#define VSC8244_INTR_MDI_XOVER_CHNG 0x0040
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#define VSC8244_INTR_FIFO_OVER_UNDER 0x0080
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#define VSC8244_INTR_FALSE_CARRIER 0x0100
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#define VSC8244_INTR_SYMBOL_ERROR 0x0200
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#define VSC8244_INTR_LINK_CHNG 0x0400
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#define VSC8244_INTR_AUTONEG_DONE 0x0800
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#define VSC8244_INTR_PAGE_RECV 0x1000
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#define VSC8244_INTR_DUPLEX_CHNG 0x2000
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#define VSC8244_INTR_SPEED_CHNG 0x4000
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#define VSC8244_INTR_AUTONEG_ERR 0x8000
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#else
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//#define VSC8244_INTR_JABBER 0x0001
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//#define VSC8244_INTR_POLARITY_CHNG 0x0002
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//#define VSC8244_INTR_BIT2 0x0004
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//#define VSC8244_INTR_BIT3 0x0008
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#define VSC8244_INTR_RX_ERR 0x0001
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#define VSC8244_INTR_MASTER_SLAVE 0x0002
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#define VSC8244_INTR_CABLE_IMPAIRED 0x0004
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#define VSC8244_INTR_FALSE_CARRIER 0x0008
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//#define VSC8244_INTR_ENG_DETECT_CHNG 0x0010
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//#define VSC8244_INTR_DOWNSHIFT 0x0020
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//#define VSC8244_INTR_MDI_XOVER_CHNG 0x0040
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//#define VSC8244_INTR_FIFO_OVER_UNDER 0x0080
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#define VSC8244_INTR_BIT4 0x0010
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#define VSC8244_INTR_FIFO_RX 0x0020
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#define VSC8244_INTR_FIFO_OVER_UNDER 0x0040
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#define VSC8244_INTR_LOCK_LOST 0x0080
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//#define VSC8244_INTR_FALSE_CARRIER 0x0100
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//#define VSC8244_INTR_SYMBOL_ERROR 0x0200
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//#define VSC8244_INTR_LINK_CHNG 0x0400
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//#define VSC8244_INTR_AUTONEG_DONE 0x0800
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#define VSC8244_INTR_SYMBOL_ERROR 0x0100
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#define VSC8244_INTR_ENG_DETECT_CHNG 0x0200
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#define VSC8244_INTR_AUTONEG_DONE 0x0400
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#define VSC8244_INTR_AUTONEG_ERR 0x0800
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//#define VSC8244_INTR_PAGE_RECV 0x1000
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//#define VSC8244_INTR_DUPLEX_CHNG 0x2000
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//#define VSC8244_INTR_SPEED_CHNG 0x4000
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//#define VSC8244_INTR_AUTONEG_ERR 0x8000
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#define VSC8244_INTR_DUPLEX_CHNG 0x1000
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#define VSC8244_INTR_LINK_CHNG 0x2000
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#define VSC8244_INTR_SPEED_CHNG 0x4000
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#define VSC8244_INTR_STATUS 0x8000
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#endif
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/* Vitesse PHY specific registers. */
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#define VSC8244_SPECIFIC_CNTRL_REGISTER 16
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#define VSC8244_SPECIFIC_STATUS_REGISTER 0x1c
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#define VSC8244_INTERRUPT_ENABLE_REGISTER 0x19
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#define VSC8244_INTERRUPT_STATUS_REGISTER 0x1a
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#define VSC8244_EXT_PHY_SPECIFIC_CNTRL_REGISTER 20
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#define VSC8244_RECV_ERR_CNTR_REGISTER 21
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#define VSC8244_RES_REGISTER 22
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#define VSC8244_GLOBAL_STATUS_REGISTER 23
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#define VSC8244_LED_CONTROL_REGISTER 24
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#define VSC8244_MANUAL_LED_OVERRIDE_REGISTER 25
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#define VSC8244_EXT_PHY_SPECIFIC_CNTRL_2_REGISTER 26
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#define VSC8244_EXT_PHY_SPECIFIC_STATUS_REGISTER 27
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#define VSC8244_VIRTUAL_CABLE_TESTER_REGISTER 28
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#define VSC8244_EXTENDED_ADDR_REGISTER 29
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#define VSC8244_EXTENDED_REGISTER 30
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/* PHY specific control register fields */
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#define S_PSCR_MDI_XOVER_MODE 5
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#define M_PSCR_MDI_XOVER_MODE 0x3
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#define V_PSCR_MDI_XOVER_MODE(x) ((x) << S_PSCR_MDI_XOVER_MODE)
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#define G_PSCR_MDI_XOVER_MODE(x) (((x) >> S_PSCR_MDI_XOVER_MODE) & M_PSCR_MDI_XOVER_MODE)
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/* Extended PHY specific control register fields */
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#define S_DOWNSHIFT_ENABLE 8
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#define V_DOWNSHIFT_ENABLE (1 << S_DOWNSHIFT_ENABLE)
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#define S_DOWNSHIFT_CNT 9
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#define M_DOWNSHIFT_CNT 0x7
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#define V_DOWNSHIFT_CNT(x) ((x) << S_DOWNSHIFT_CNT)
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#define G_DOWNSHIFT_CNT(x) (((x) >> S_DOWNSHIFT_CNT) & M_DOWNSHIFT_CNT)
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/* PHY specific status register fields */
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#define S_PSSR_JABBER 0
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#define V_PSSR_JABBER (1 << S_PSSR_JABBER)
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#define S_PSSR_POLARITY 1
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#define V_PSSR_POLARITY (1 << S_PSSR_POLARITY)
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#define S_PSSR_RX_PAUSE 2
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#define V_PSSR_RX_PAUSE (1 << S_PSSR_RX_PAUSE)
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#define S_PSSR_TX_PAUSE 3
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#define V_PSSR_TX_PAUSE (1 << S_PSSR_TX_PAUSE)
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#define S_PSSR_ENERGY_DETECT 4
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#define V_PSSR_ENERGY_DETECT (1 << S_PSSR_ENERGY_DETECT)
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#define S_PSSR_DOWNSHIFT_STATUS 5
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#define V_PSSR_DOWNSHIFT_STATUS (1 << S_PSSR_DOWNSHIFT_STATUS)
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#define S_PSSR_MDI 6
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#define V_PSSR_MDI (1 << S_PSSR_MDI)
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#define S_PSSR_CABLE_LEN 7
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#define M_PSSR_CABLE_LEN 0x7
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#define V_PSSR_CABLE_LEN(x) ((x) << S_PSSR_CABLE_LEN)
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#define G_PSSR_CABLE_LEN(x) (((x) >> S_PSSR_CABLE_LEN) & M_PSSR_CABLE_LEN)
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//#define S_PSSR_LINK 10
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//#define S_PSSR_LINK 13
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#define S_PSSR_LINK 2
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#define V_PSSR_LINK (1 << S_PSSR_LINK)
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//#define S_PSSR_STATUS_RESOLVED 11
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//#define S_PSSR_STATUS_RESOLVED 10
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#define S_PSSR_STATUS_RESOLVED 15
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#define V_PSSR_STATUS_RESOLVED (1 << S_PSSR_STATUS_RESOLVED)
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#define S_PSSR_PAGE_RECEIVED 12
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#define V_PSSR_PAGE_RECEIVED (1 << S_PSSR_PAGE_RECEIVED)
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//#define S_PSSR_DUPLEX 13
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//#define S_PSSR_DUPLEX 12
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#define S_PSSR_DUPLEX 5
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#define V_PSSR_DUPLEX (1 << S_PSSR_DUPLEX)
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//#define S_PSSR_SPEED 14
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//#define S_PSSR_SPEED 14
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#define S_PSSR_SPEED 3
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#define M_PSSR_SPEED 0x3
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#define V_PSSR_SPEED(x) ((x) << S_PSSR_SPEED)
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#define G_PSSR_SPEED(x) (((x) >> S_PSSR_SPEED) & M_PSSR_SPEED)
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#endif
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