forked from luck/tmp_suning_uos_patched
a5e6f64dda
Signed-off-by: Harvey Harrison <harvey.harrison@gmail.com> Signed-off-by: Stefan Richter <stefanr@s5r6.in-berlin.de>
100 lines
2.6 KiB
C
100 lines
2.6 KiB
C
#ifndef _IEEE1394_CSR_H
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#define _IEEE1394_CSR_H
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#include <linux/spinlock_types.h>
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#include "csr1212.h"
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#include "ieee1394_types.h"
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#define CSR_REGISTER_BASE 0xfffff0000000ULL
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/* register offsets relative to CSR_REGISTER_BASE */
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#define CSR_STATE_CLEAR 0x0
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#define CSR_STATE_SET 0x4
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#define CSR_NODE_IDS 0x8
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#define CSR_RESET_START 0xc
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#define CSR_SPLIT_TIMEOUT_HI 0x18
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#define CSR_SPLIT_TIMEOUT_LO 0x1c
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#define CSR_CYCLE_TIME 0x200
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#define CSR_BUS_TIME 0x204
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#define CSR_BUSY_TIMEOUT 0x210
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#define CSR_BUS_MANAGER_ID 0x21c
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#define CSR_BANDWIDTH_AVAILABLE 0x220
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#define CSR_CHANNELS_AVAILABLE 0x224
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#define CSR_CHANNELS_AVAILABLE_HI 0x224
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#define CSR_CHANNELS_AVAILABLE_LO 0x228
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#define CSR_BROADCAST_CHANNEL 0x234
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#define CSR_CONFIG_ROM 0x400
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#define CSR_CONFIG_ROM_END 0x800
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#define CSR_FCP_COMMAND 0xB00
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#define CSR_FCP_RESPONSE 0xD00
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#define CSR_FCP_END 0xF00
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#define CSR_TOPOLOGY_MAP 0x1000
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#define CSR_TOPOLOGY_MAP_END 0x1400
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#define CSR_SPEED_MAP 0x2000
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#define CSR_SPEED_MAP_END 0x3000
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/* IEEE 1394 bus specific Configuration ROM Key IDs */
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#define IEEE1394_KV_ID_POWER_REQUIREMENTS (0x30)
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/* IEEE 1394 Bus Information Block specifics */
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#define CSR_BUS_INFO_SIZE (5 * sizeof(quadlet_t))
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#define CSR_IRMC_SHIFT 31
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#define CSR_CMC_SHIFT 30
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#define CSR_ISC_SHIFT 29
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#define CSR_BMC_SHIFT 28
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#define CSR_PMC_SHIFT 27
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#define CSR_CYC_CLK_ACC_SHIFT 16
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#define CSR_MAX_REC_SHIFT 12
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#define CSR_MAX_ROM_SHIFT 8
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#define CSR_GENERATION_SHIFT 4
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static inline void csr_set_bus_info_generation(struct csr1212_csr *csr, u8 gen)
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{
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csr->bus_info_data[2] &= ~cpu_to_be32(0xf << CSR_GENERATION_SHIFT);
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csr->bus_info_data[2] |= cpu_to_be32((u32)gen << CSR_GENERATION_SHIFT);
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}
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struct csr_control {
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spinlock_t lock;
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quadlet_t state;
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quadlet_t node_ids;
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quadlet_t split_timeout_hi, split_timeout_lo;
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unsigned long expire; /* Calculated from split_timeout */
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quadlet_t cycle_time;
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quadlet_t bus_time;
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quadlet_t bus_manager_id;
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quadlet_t bandwidth_available;
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quadlet_t channels_available_hi, channels_available_lo;
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quadlet_t broadcast_channel;
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/* Bus Info */
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quadlet_t guid_hi, guid_lo;
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u8 cyc_clk_acc;
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u8 max_rec;
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u8 max_rom;
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u8 generation; /* Only use values between 0x2 and 0xf */
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u8 lnk_spd;
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unsigned long gen_timestamp[16];
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struct csr1212_csr *rom;
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quadlet_t topology_map[256];
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quadlet_t speed_map[1024];
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};
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extern struct csr1212_bus_ops csr_bus_ops;
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int init_csr(void);
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void cleanup_csr(void);
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/* hpsb_update_config_rom() is deprecated */
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struct hpsb_host;
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int hpsb_update_config_rom(struct hpsb_host *host, const quadlet_t *new_rom,
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size_t size, unsigned char rom_version);
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#endif /* _IEEE1394_CSR_H */
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