forked from luck/tmp_suning_uos_patched
6a39dd6222
Patch from Daniel Jacobowitz
The ARM kernel has several uses of asm("foo%?"). %? is a GCC internal
modifier used to output conditional execution predicates. However, no
version of GCC supports conditionalizing asm statements. GCC 4.2 will
correctly expand %? to the empty string in user asms. Earlier versions may
reuse the condition from the previous instruction. In 'if (foo) asm
("bar%?");' this is somewhat likely to be right... but not reliable.
So, the only safe thing to do is to remove the uses of %?. I believe
the tlbflush.h occurances were supposed to be removed before, based
on the comment about %? not working at the top of that file.
Old versions of GCC could omit branches around user asms if the asm didn't
mark the condition codes as clobbered. This problem hasn't been seen on any
recent (3.x or 4.x) GCC, but it could theoretically happen. So, where
%? was removed a cc clobber was added.
Signed-off-by: Daniel Jacobowitz <dan@codesourcery.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
89 lines
2.8 KiB
C
89 lines
2.8 KiB
C
/*
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* linux/arch/arm/vfp/vfpinstr.h
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*
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* Copyright (C) 2004 ARM Limited.
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* Written by Deep Blue Solutions Limited.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* VFP instruction masks.
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*/
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#define INST_CPRTDO(inst) (((inst) & 0x0f000000) == 0x0e000000)
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#define INST_CPRT(inst) ((inst) & (1 << 4))
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#define INST_CPRT_L(inst) ((inst) & (1 << 20))
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#define INST_CPRT_Rd(inst) (((inst) & (15 << 12)) >> 12)
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#define INST_CPRT_OP(inst) (((inst) >> 21) & 7)
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#define INST_CPNUM(inst) ((inst) & 0xf00)
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#define CPNUM(cp) ((cp) << 8)
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#define FOP_MASK (0x00b00040)
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#define FOP_FMAC (0x00000000)
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#define FOP_FNMAC (0x00000040)
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#define FOP_FMSC (0x00100000)
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#define FOP_FNMSC (0x00100040)
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#define FOP_FMUL (0x00200000)
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#define FOP_FNMUL (0x00200040)
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#define FOP_FADD (0x00300000)
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#define FOP_FSUB (0x00300040)
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#define FOP_FDIV (0x00800000)
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#define FOP_EXT (0x00b00040)
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#define FOP_TO_IDX(inst) ((inst & 0x00b00000) >> 20 | (inst & (1 << 6)) >> 4)
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#define FEXT_MASK (0x000f0080)
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#define FEXT_FCPY (0x00000000)
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#define FEXT_FABS (0x00000080)
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#define FEXT_FNEG (0x00010000)
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#define FEXT_FSQRT (0x00010080)
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#define FEXT_FCMP (0x00040000)
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#define FEXT_FCMPE (0x00040080)
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#define FEXT_FCMPZ (0x00050000)
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#define FEXT_FCMPEZ (0x00050080)
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#define FEXT_FCVT (0x00070080)
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#define FEXT_FUITO (0x00080000)
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#define FEXT_FSITO (0x00080080)
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#define FEXT_FTOUI (0x000c0000)
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#define FEXT_FTOUIZ (0x000c0080)
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#define FEXT_FTOSI (0x000d0000)
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#define FEXT_FTOSIZ (0x000d0080)
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#define FEXT_TO_IDX(inst) ((inst & 0x000f0000) >> 15 | (inst & (1 << 7)) >> 7)
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#define vfp_get_sd(inst) ((inst & 0x0000f000) >> 11 | (inst & (1 << 22)) >> 22)
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#define vfp_get_dd(inst) ((inst & 0x0000f000) >> 12)
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#define vfp_get_sm(inst) ((inst & 0x0000000f) << 1 | (inst & (1 << 5)) >> 5)
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#define vfp_get_dm(inst) ((inst & 0x0000000f))
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#define vfp_get_sn(inst) ((inst & 0x000f0000) >> 15 | (inst & (1 << 7)) >> 7)
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#define vfp_get_dn(inst) ((inst & 0x000f0000) >> 16)
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#define vfp_single(inst) (((inst) & 0x0000f00) == 0xa00)
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#define FPSCR_N (1 << 31)
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#define FPSCR_Z (1 << 30)
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#define FPSCR_C (1 << 29)
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#define FPSCR_V (1 << 28)
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/*
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* Since we aren't building with -mfpu=vfp, we need to code
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* these instructions using their MRC/MCR equivalents.
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*/
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#define vfpreg(_vfp_) #_vfp_
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#define fmrx(_vfp_) ({ \
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u32 __v; \
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asm("mrc p10, 7, %0, " vfpreg(_vfp_) ", cr0, 0 @ fmrx %0, " #_vfp_ \
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: "=r" (__v) : : "cc"); \
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__v; \
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})
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#define fmxr(_vfp_,_var_) \
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asm("mcr p10, 7, %0, " vfpreg(_vfp_) ", cr0, 0 @ fmxr " #_vfp_ ", %0" \
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: : "r" (_var_) : "cc")
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u32 vfp_single_cpdo(u32 inst, u32 fpscr);
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u32 vfp_single_cprt(u32 inst, u32 fpscr, struct pt_regs *regs);
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u32 vfp_double_cpdo(u32 inst, u32 fpscr);
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