forked from luck/tmp_suning_uos_patched
d6b0bf213b
Patch from Ben Dooks Add the definitions for the S3C2410_CLKSLOW registers to the header files, and show the values when the system starts up Signed-off-by: Ben Dooks <ben-linux@fluff.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
130 lines
4.3 KiB
C
130 lines
4.3 KiB
C
/* linux/include/asm/arch-s3c2410/regs-clock.h
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*
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* Copyright (c) 2003,2004,2005 Simtec Electronics <linux@simtec.co.uk>
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* http://armlinux.simtec.co.uk/
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* S3C2410 clock register definitions
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*
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* Changelog:
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* 18-Aug-2004 Ben Dooks Added 2440 definitions
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* 08-Aug-2004 Herbert Pötzl Added CLKCON definitions
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* 19-06-2003 Ben Dooks Created file
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* 12-03-2004 Ben Dooks Updated include protection
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* 29-Sep-2004 Ben Dooks Fixed usage for assembly inclusion
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* 10-Feb-2005 Ben Dooks Fixed CAMDIVN address (Guillaume Gourat)
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* 10-Mar-2005 Lucas Villa Real Changed S3C2410_VA to S3C24XX_VA
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* 27-Aug-2005 Ben Dooks Add clock-slow info
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*/
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#ifndef __ASM_ARM_REGS_CLOCK
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#define __ASM_ARM_REGS_CLOCK "$Id: clock.h,v 1.4 2003/04/30 14:50:51 ben Exp $"
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#define S3C2410_CLKREG(x) ((x) + S3C24XX_VA_CLKPWR)
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#define S3C2410_PLLVAL(_m,_p,_s) ((_m) << 12 | ((_p) << 4) | ((_s)))
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#define S3C2410_LOCKTIME S3C2410_CLKREG(0x00)
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#define S3C2410_MPLLCON S3C2410_CLKREG(0x04)
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#define S3C2410_UPLLCON S3C2410_CLKREG(0x08)
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#define S3C2410_CLKCON S3C2410_CLKREG(0x0C)
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#define S3C2410_CLKSLOW S3C2410_CLKREG(0x10)
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#define S3C2410_CLKDIVN S3C2410_CLKREG(0x14)
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#define S3C2410_CLKCON_IDLE (1<<2)
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#define S3C2410_CLKCON_POWER (1<<3)
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#define S3C2410_CLKCON_NAND (1<<4)
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#define S3C2410_CLKCON_LCDC (1<<5)
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#define S3C2410_CLKCON_USBH (1<<6)
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#define S3C2410_CLKCON_USBD (1<<7)
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#define S3C2410_CLKCON_PWMT (1<<8)
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#define S3C2410_CLKCON_SDI (1<<9)
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#define S3C2410_CLKCON_UART0 (1<<10)
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#define S3C2410_CLKCON_UART1 (1<<11)
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#define S3C2410_CLKCON_UART2 (1<<12)
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#define S3C2410_CLKCON_GPIO (1<<13)
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#define S3C2410_CLKCON_RTC (1<<14)
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#define S3C2410_CLKCON_ADC (1<<15)
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#define S3C2410_CLKCON_IIC (1<<16)
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#define S3C2410_CLKCON_IIS (1<<17)
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#define S3C2410_CLKCON_SPI (1<<18)
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#define S3C2410_PLLCON_MDIVSHIFT 12
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#define S3C2410_PLLCON_PDIVSHIFT 4
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#define S3C2410_PLLCON_SDIVSHIFT 0
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#define S3C2410_PLLCON_MDIVMASK ((1<<(1+(19-12)))-1)
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#define S3C2410_PLLCON_PDIVMASK ((1<<5)-1)
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#define S3C2410_PLLCON_SDIVMASK 3
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/* DCLKCON register addresses in gpio.h */
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#define S3C2410_DCLKCON_DCLK0EN (1<<0)
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#define S3C2410_DCLKCON_DCLK0_PCLK (0<<1)
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#define S3C2410_DCLKCON_DCLK0_UCLK (1<<1)
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#define S3C2410_DCLKCON_DCLK0_DIV(x) (((x) - 1 )<<4)
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#define S3C2410_DCLKCON_DCLK0_CMP(x) (((x) - 1 )<<8)
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#define S3C2410_DCLKCON_DCLK1EN (1<<16)
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#define S3C2410_DCLKCON_DCLK1_PCLK (0<<17)
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#define S3C2410_DCLKCON_DCLK1_UCLK (1<<17)
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#define S3C2410_DCLKCON_DCLK1_DIV(x) (((x) - 1) <<20)
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#define S3C2410_CLKDIVN_PDIVN (1<<0)
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#define S3C2410_CLKDIVN_HDIVN (1<<1)
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#define S3C2410_CLKSLOW_UCLK_OFF (1<<7)
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#define S3C2410_CLKSLOW_MPLL_OFF (1<<5)
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#define S3C2410_CLKSLOW_SLOW (1<<4)
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#define S3C2410_CLKSLOW_SLOWVAL(x) (x)
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#define S3C2410_CLKSLOW_GET_SLOWVAL(x) ((x) & 7)
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#ifndef __ASSEMBLY__
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static inline unsigned int
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s3c2410_get_pll(int pllval, int baseclk)
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{
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int mdiv, pdiv, sdiv;
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mdiv = pllval >> S3C2410_PLLCON_MDIVSHIFT;
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pdiv = pllval >> S3C2410_PLLCON_PDIVSHIFT;
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sdiv = pllval >> S3C2410_PLLCON_SDIVSHIFT;
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mdiv &= S3C2410_PLLCON_MDIVMASK;
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pdiv &= S3C2410_PLLCON_PDIVMASK;
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sdiv &= S3C2410_PLLCON_SDIVMASK;
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return (baseclk * (mdiv + 8)) / ((pdiv + 2) << sdiv);
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}
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#endif /* __ASSEMBLY__ */
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#ifdef CONFIG_CPU_S3C2440
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/* extra registers */
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#define S3C2440_CAMDIVN S3C2410_CLKREG(0x18)
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#define S3C2440_CLKCON_CAMERA (1<<19)
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#define S3C2440_CLKCON_AC97 (1<<20)
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#define S3C2440_CLKDIVN_PDIVN (1<<0)
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#define S3C2440_CLKDIVN_HDIVN_MASK (3<<1)
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#define S3C2440_CLKDIVN_HDIVN_1 (0<<1)
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#define S3C2440_CLKDIVN_HDIVN_2 (1<<1)
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#define S3C2440_CLKDIVN_HDIVN_4_8 (2<<1)
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#define S3C2440_CLKDIVN_HDIVN_3_6 (3<<1)
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#define S3C2440_CLKDIVN_UCLK (1<<3)
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#define S3C2440_CAMDIVN_CAMCLK_MASK (0xf<<0)
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#define S3C2440_CAMDIVN_CAMCLK_SEL (1<<4)
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#define S3C2440_CAMDIVN_HCLK3_HALF (1<<8)
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#define S3C2440_CAMDIVN_HCLK4_HALF (1<<9)
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#define S3C2440_CAMDIVN_DVSEN (1<<12)
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#endif /* CONFIG_CPU_S3C2440 */
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#endif /* __ASM_ARM_REGS_CLOCK */
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