forked from luck/tmp_suning_uos_patched
9e39ffeff6
Commit 8b798c4d16 broke
alchemy build, fix it. Pointed out by Adrian Bunk.
Signed-off-by: Manuel Lauss <mano@roarinelk.homelinux.net>
Signed-off-by: Jean Delvare <khali@linux-fr.org>
224 lines
6.3 KiB
C
224 lines
6.3 KiB
C
/*
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* AMD Alchemy DB1x00 Reference Boards
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*
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* Copyright 2001 MontaVista Software Inc.
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* Author: MontaVista Software, Inc.
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* ppopov@mvista.com or source@mvista.com
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* Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org)
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*
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* ########################################################################
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*
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* This program is free software; you can distribute it and/or modify it
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* under the terms of the GNU General Public License (Version 2) as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
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*
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* ########################################################################
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*
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*
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*/
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#ifndef __ASM_DB1X00_H
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#define __ASM_DB1X00_H
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#include <asm/mach-au1x00/au1xxx_psc.h>
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#ifdef CONFIG_MIPS_DB1550
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#define DBDMA_AC97_TX_CHAN DSCR_CMD0_PSC1_TX
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#define DBDMA_AC97_RX_CHAN DSCR_CMD0_PSC1_RX
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#define DBDMA_I2S_TX_CHAN DSCR_CMD0_PSC3_TX
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#define DBDMA_I2S_RX_CHAN DSCR_CMD0_PSC3_RX
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#define SPI_PSC_BASE PSC0_BASE_ADDR
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#define AC97_PSC_BASE PSC1_BASE_ADDR
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#define SMBUS_PSC_BASE PSC2_BASE_ADDR
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#define I2S_PSC_BASE PSC3_BASE_ADDR
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#define BCSR_KSEG1_ADDR 0xAF000000
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#define NAND_PHYS_ADDR 0x20000000
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#else
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#define BCSR_KSEG1_ADDR 0xAE000000
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#endif
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/*
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* Overlay data structure of the Db1x00 board registers.
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* Registers located at physical 0E0000xx, KSEG1 0xAE0000xx
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*/
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typedef volatile struct
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{
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/*00*/ unsigned short whoami;
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unsigned short reserved0;
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/*04*/ unsigned short status;
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unsigned short reserved1;
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/*08*/ unsigned short switches;
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unsigned short reserved2;
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/*0C*/ unsigned short resets;
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unsigned short reserved3;
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/*10*/ unsigned short pcmcia;
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unsigned short reserved4;
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/*14*/ unsigned short specific;
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unsigned short reserved5;
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/*18*/ unsigned short leds;
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unsigned short reserved6;
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/*1C*/ unsigned short swreset;
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unsigned short reserved7;
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} BCSR;
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/*
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* Register/mask bit definitions for the BCSRs
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*/
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#define BCSR_WHOAMI_DCID 0x000F
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#define BCSR_WHOAMI_CPLD 0x00F0
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#define BCSR_WHOAMI_BOARD 0x0F00
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#define BCSR_STATUS_PC0VS 0x0003
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#define BCSR_STATUS_PC1VS 0x000C
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#define BCSR_STATUS_PC0FI 0x0010
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#define BCSR_STATUS_PC1FI 0x0020
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#define BCSR_STATUS_FLASHBUSY 0x0100
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#define BCSR_STATUS_ROMBUSY 0x0400
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#define BCSR_STATUS_SWAPBOOT 0x2000
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#define BCSR_STATUS_FLASHDEN 0xC000
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#define BCSR_SWITCHES_DIP 0x00FF
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#define BCSR_SWITCHES_DIP_1 0x0080
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#define BCSR_SWITCHES_DIP_2 0x0040
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#define BCSR_SWITCHES_DIP_3 0x0020
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#define BCSR_SWITCHES_DIP_4 0x0010
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#define BCSR_SWITCHES_DIP_5 0x0008
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#define BCSR_SWITCHES_DIP_6 0x0004
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#define BCSR_SWITCHES_DIP_7 0x0002
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#define BCSR_SWITCHES_DIP_8 0x0001
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#define BCSR_SWITCHES_ROTARY 0x0F00
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#define BCSR_RESETS_PHY0 0x0001
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#define BCSR_RESETS_PHY1 0x0002
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#define BCSR_RESETS_DC 0x0004
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#define BCSR_RESETS_FIR_SEL 0x2000
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#define BCSR_RESETS_IRDA_MODE_MASK 0xC000
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#define BCSR_RESETS_IRDA_MODE_FULL 0x0000
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#define BCSR_RESETS_IRDA_MODE_OFF 0x4000
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#define BCSR_RESETS_IRDA_MODE_2_3 0x8000
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#define BCSR_RESETS_IRDA_MODE_1_3 0xC000
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#define BCSR_PCMCIA_PC0VPP 0x0003
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#define BCSR_PCMCIA_PC0VCC 0x000C
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#define BCSR_PCMCIA_PC0DRVEN 0x0010
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#define BCSR_PCMCIA_PC0RST 0x0080
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#define BCSR_PCMCIA_PC1VPP 0x0300
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#define BCSR_PCMCIA_PC1VCC 0x0C00
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#define BCSR_PCMCIA_PC1DRVEN 0x1000
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#define BCSR_PCMCIA_PC1RST 0x8000
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#define BCSR_BOARD_PCIM66EN 0x0001
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#define BCSR_BOARD_SD0_PWR 0x0040
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#define BCSR_BOARD_SD1_PWR 0x0080
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#define BCSR_BOARD_PCIM33 0x0100
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#define BCSR_BOARD_GPIO200RST 0x0400
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#define BCSR_BOARD_PCICFG 0x1000
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#define BCSR_BOARD_SD0_WP 0x4000
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#define BCSR_BOARD_SD1_WP 0x8000
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#define BCSR_LEDS_DECIMALS 0x0003
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#define BCSR_LEDS_LED0 0x0100
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#define BCSR_LEDS_LED1 0x0200
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#define BCSR_LEDS_LED2 0x0400
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#define BCSR_LEDS_LED3 0x0800
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#define BCSR_SWRESET_RESET 0x0080
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/* PCMCIA Db1x00 specific defines */
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#define PCMCIA_MAX_SOCK 1
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#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK+1)
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/* VPP/VCC */
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#define SET_VCC_VPP(VCC, VPP, SLOT)\
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((((VCC)<<2) | ((VPP)<<0)) << ((SLOT)*8))
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/* SD controller macros */
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/*
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* Detect card.
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*/
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#define mmc_card_inserted(_n_, _res_) \
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do { \
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BCSR * const bcsr = (BCSR *)0xAE000000; \
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unsigned long mmc_wp, board_specific; \
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if ((_n_)) { \
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mmc_wp = BCSR_BOARD_SD1_WP; \
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} else { \
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mmc_wp = BCSR_BOARD_SD0_WP; \
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} \
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board_specific = au_readl((unsigned long)(&bcsr->specific)); \
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if (!(board_specific & mmc_wp)) {/* low means card present */ \
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*(int *)(_res_) = 1; \
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} else { \
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*(int *)(_res_) = 0; \
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} \
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} while (0)
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/*
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* Apply power to card slot(s).
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*/
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#define mmc_power_on(_n_) \
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do { \
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BCSR * const bcsr = (BCSR *)0xAE000000; \
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unsigned long mmc_pwr, mmc_wp, board_specific; \
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if ((_n_)) { \
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mmc_pwr = BCSR_BOARD_SD1_PWR; \
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mmc_wp = BCSR_BOARD_SD1_WP; \
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} else { \
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mmc_pwr = BCSR_BOARD_SD0_PWR; \
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mmc_wp = BCSR_BOARD_SD0_WP; \
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} \
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board_specific = au_readl((unsigned long)(&bcsr->specific)); \
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if (!(board_specific & mmc_wp)) {/* low means card present */ \
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board_specific |= mmc_pwr; \
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au_writel(board_specific, (int)(&bcsr->specific)); \
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au_sync(); \
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} \
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} while (0)
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/* NAND defines */
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/* Timing values as described in databook, * ns value stripped of
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* lower 2 bits.
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* These defines are here rather than an SOC1550 generic file because
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* the parts chosen on another board may be different and may require
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* different timings.
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*/
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#define NAND_T_H (18 >> 2)
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#define NAND_T_PUL (30 >> 2)
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#define NAND_T_SU (30 >> 2)
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#define NAND_T_WH (30 >> 2)
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/* Bitfield shift amounts */
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#define NAND_T_H_SHIFT 0
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#define NAND_T_PUL_SHIFT 4
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#define NAND_T_SU_SHIFT 8
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#define NAND_T_WH_SHIFT 12
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#define NAND_TIMING ((NAND_T_H & 0xF) << NAND_T_H_SHIFT) | \
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((NAND_T_PUL & 0xF) << NAND_T_PUL_SHIFT) | \
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((NAND_T_SU & 0xF) << NAND_T_SU_SHIFT) | \
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((NAND_T_WH & 0xF) << NAND_T_WH_SHIFT)
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#define NAND_CS 1
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/* should be done by yamon */
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#define NAND_STCFG 0x00400005 /* 8-bit NAND */
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#define NAND_STTIME 0x00007774 /* valid for 396MHz SD=2 only */
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#define NAND_STADDR 0x12000FFF /* physical address 0x20000000 */
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#endif /* __ASM_DB1X00_H */
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