forked from luck/tmp_suning_uos_patched
5f8b6c3485
* Add ->mwdma_mask and ->swdma_mask to ide_pci_device_t.
* Set ide_hwif_t DMA masks using DMA masks from ide_pci_device_t in
setup-pci.c::ide_pci_setup_ports() (iff DMA base is valid and ->init_hwif
method may still override them).
* Convert IDE PCI host drivers to use ide_pci_device_t DMA masks.
While at it:
* Use ATA_{UDMA,MWDMA,SWDMA}* defines.
* hpt34x.c: add separate ide_pci_device_t instances for HPT343 and HPT345.
* serverworks.c: fix DMA masks being set before checking DMA base.
v2:
* Add missing masks to DECLARE_GENERIC_PCI_DEV() macro.
Signed-off-by: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
511 lines
14 KiB
C
511 lines
14 KiB
C
/*
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* linux/drivers/ide/pci/pdc202xx_old.c Version 0.52 Aug 27, 2007
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*
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* Copyright (C) 1998-2002 Andre Hedrick <andre@linux-ide.org>
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* Copyright (C) 2006-2007 MontaVista Software, Inc.
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* Copyright (C) 2007 Bartlomiej Zolnierkiewicz
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*
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* Promise Ultra33 cards with BIOS v1.20 through 1.28 will need this
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* compiled into the kernel if you have more than one card installed.
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* Note that BIOS v1.29 is reported to fix the problem. Since this is
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* safe chipset tuning, including this support is harmless
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*
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* Promise Ultra66 cards with BIOS v1.11 this
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* compiled into the kernel if you have more than one card installed.
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*
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* Promise Ultra100 cards.
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*
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* The latest chipset code will support the following ::
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* Three Ultra33 controllers and 12 drives.
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* 8 are UDMA supported and 4 are limited to DMA mode 2 multi-word.
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* The 8/4 ratio is a BIOS code limit by promise.
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*
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* UNLESS you enable "CONFIG_PDC202XX_BURST"
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*
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*/
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/*
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* Portions Copyright (C) 1999 Promise Technology, Inc.
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* Author: Frank Tiernan (frankt@promise.com)
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* Released under terms of General Public License
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*/
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#include <linux/types.h>
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/delay.h>
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#include <linux/timer.h>
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#include <linux/mm.h>
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#include <linux/ioport.h>
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#include <linux/blkdev.h>
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#include <linux/hdreg.h>
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#include <linux/interrupt.h>
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#include <linux/pci.h>
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#include <linux/init.h>
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#include <linux/ide.h>
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#include <asm/io.h>
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#include <asm/irq.h>
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#define PDC202XX_DEBUG_DRIVE_INFO 0
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static const char *pdc_quirk_drives[] = {
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"QUANTUM FIREBALLlct08 08",
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"QUANTUM FIREBALLP KA6.4",
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"QUANTUM FIREBALLP KA9.1",
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"QUANTUM FIREBALLP LM20.4",
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"QUANTUM FIREBALLP KX13.6",
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"QUANTUM FIREBALLP KX20.5",
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"QUANTUM FIREBALLP KX27.3",
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"QUANTUM FIREBALLP LM20.5",
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NULL
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};
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static void pdc_old_disable_66MHz_clock(ide_hwif_t *);
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static void pdc202xx_set_mode(ide_drive_t *drive, const u8 speed)
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{
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ide_hwif_t *hwif = HWIF(drive);
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struct pci_dev *dev = hwif->pci_dev;
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u8 drive_pci = 0x60 + (drive->dn << 2);
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u8 AP = 0, BP = 0, CP = 0;
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u8 TA = 0, TB = 0, TC = 0;
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#if PDC202XX_DEBUG_DRIVE_INFO
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u32 drive_conf = 0;
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pci_read_config_dword(dev, drive_pci, &drive_conf);
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#endif
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/*
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* TODO: do this once per channel
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*/
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if (dev->device != PCI_DEVICE_ID_PROMISE_20246)
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pdc_old_disable_66MHz_clock(hwif);
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pci_read_config_byte(dev, drive_pci, &AP);
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pci_read_config_byte(dev, drive_pci + 1, &BP);
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pci_read_config_byte(dev, drive_pci + 2, &CP);
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switch(speed) {
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case XFER_UDMA_5:
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case XFER_UDMA_4: TB = 0x20; TC = 0x01; break;
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case XFER_UDMA_2: TB = 0x20; TC = 0x01; break;
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case XFER_UDMA_3:
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case XFER_UDMA_1: TB = 0x40; TC = 0x02; break;
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case XFER_UDMA_0:
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case XFER_MW_DMA_2: TB = 0x60; TC = 0x03; break;
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case XFER_MW_DMA_1: TB = 0x60; TC = 0x04; break;
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case XFER_MW_DMA_0: TB = 0xE0; TC = 0x0F; break;
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case XFER_PIO_4: TA = 0x01; TB = 0x04; break;
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case XFER_PIO_3: TA = 0x02; TB = 0x06; break;
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case XFER_PIO_2: TA = 0x03; TB = 0x08; break;
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case XFER_PIO_1: TA = 0x05; TB = 0x0C; break;
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case XFER_PIO_0:
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default: TA = 0x09; TB = 0x13; break;
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}
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if (speed < XFER_SW_DMA_0) {
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/*
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* preserve SYNC_INT / ERDDY_EN bits while clearing
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* Prefetch_EN / IORDY_EN / PA[3:0] bits of register A
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*/
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AP &= ~0x3f;
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if (drive->id->capability & 4)
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AP |= 0x20; /* set IORDY_EN bit */
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if (drive->media == ide_disk)
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AP |= 0x10; /* set Prefetch_EN bit */
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/* clear PB[4:0] bits of register B */
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BP &= ~0x1f;
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pci_write_config_byte(dev, drive_pci, AP | TA);
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pci_write_config_byte(dev, drive_pci + 1, BP | TB);
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} else {
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/* clear MB[2:0] bits of register B */
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BP &= ~0xe0;
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/* clear MC[3:0] bits of register C */
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CP &= ~0x0f;
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pci_write_config_byte(dev, drive_pci + 1, BP | TB);
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pci_write_config_byte(dev, drive_pci + 2, CP | TC);
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}
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#if PDC202XX_DEBUG_DRIVE_INFO
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printk(KERN_DEBUG "%s: %s drive%d 0x%08x ",
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drive->name, ide_xfer_verbose(speed),
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drive->dn, drive_conf);
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pci_read_config_dword(dev, drive_pci, &drive_conf);
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printk("0x%08x\n", drive_conf);
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#endif
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}
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static void pdc202xx_set_pio_mode(ide_drive_t *drive, const u8 pio)
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{
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pdc202xx_set_mode(drive, XFER_PIO_0 + pio);
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}
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static u8 pdc202xx_old_cable_detect (ide_hwif_t *hwif)
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{
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u16 CIS = 0, mask = (hwif->channel) ? (1<<11) : (1<<10);
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pci_read_config_word(hwif->pci_dev, 0x50, &CIS);
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return (CIS & mask) ? ATA_CBL_PATA40 : ATA_CBL_PATA80;
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}
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/*
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* Set the control register to use the 66MHz system
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* clock for UDMA 3/4/5 mode operation when necessary.
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*
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* FIXME: this register is shared by both channels, some locking is needed
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*
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* It may also be possible to leave the 66MHz clock on
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* and readjust the timing parameters.
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*/
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static void pdc_old_enable_66MHz_clock(ide_hwif_t *hwif)
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{
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unsigned long clock_reg = hwif->dma_master + 0x11;
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u8 clock = inb(clock_reg);
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outb(clock | (hwif->channel ? 0x08 : 0x02), clock_reg);
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}
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static void pdc_old_disable_66MHz_clock(ide_hwif_t *hwif)
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{
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unsigned long clock_reg = hwif->dma_master + 0x11;
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u8 clock = inb(clock_reg);
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outb(clock & ~(hwif->channel ? 0x08 : 0x02), clock_reg);
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}
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static int pdc202xx_quirkproc (ide_drive_t *drive)
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{
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const char **list, *model = drive->id->model;
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for (list = pdc_quirk_drives; *list != NULL; list++)
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if (strstr(model, *list) != NULL)
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return 2;
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return 0;
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}
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static void pdc202xx_old_ide_dma_start(ide_drive_t *drive)
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{
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if (drive->current_speed > XFER_UDMA_2)
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pdc_old_enable_66MHz_clock(drive->hwif);
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if (drive->media != ide_disk || drive->addressing == 1) {
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struct request *rq = HWGROUP(drive)->rq;
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ide_hwif_t *hwif = HWIF(drive);
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unsigned long high_16 = hwif->dma_master;
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unsigned long atapi_reg = high_16 + (hwif->channel ? 0x24 : 0x20);
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u32 word_count = 0;
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u8 clock = inb(high_16 + 0x11);
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outb(clock | (hwif->channel ? 0x08 : 0x02), high_16 + 0x11);
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word_count = (rq->nr_sectors << 8);
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word_count = (rq_data_dir(rq) == READ) ?
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word_count | 0x05000000 :
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word_count | 0x06000000;
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outl(word_count, atapi_reg);
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}
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ide_dma_start(drive);
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}
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static int pdc202xx_old_ide_dma_end(ide_drive_t *drive)
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{
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if (drive->media != ide_disk || drive->addressing == 1) {
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ide_hwif_t *hwif = HWIF(drive);
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unsigned long high_16 = hwif->dma_master;
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unsigned long atapi_reg = high_16 + (hwif->channel ? 0x24 : 0x20);
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u8 clock = 0;
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outl(0, atapi_reg); /* zero out extra */
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clock = inb(high_16 + 0x11);
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outb(clock & ~(hwif->channel ? 0x08:0x02), high_16 + 0x11);
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}
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if (drive->current_speed > XFER_UDMA_2)
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pdc_old_disable_66MHz_clock(drive->hwif);
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return __ide_dma_end(drive);
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}
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static int pdc202xx_old_ide_dma_test_irq(ide_drive_t *drive)
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{
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ide_hwif_t *hwif = HWIF(drive);
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unsigned long high_16 = hwif->dma_master;
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u8 dma_stat = inb(hwif->dma_status);
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u8 sc1d = inb(high_16 + 0x001d);
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if (hwif->channel) {
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/* bit7: Error, bit6: Interrupting, bit5: FIFO Full, bit4: FIFO Empty */
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if ((sc1d & 0x50) == 0x50)
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goto somebody_else;
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else if ((sc1d & 0x40) == 0x40)
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return (dma_stat & 4) == 4;
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} else {
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/* bit3: Error, bit2: Interrupting, bit1: FIFO Full, bit0: FIFO Empty */
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if ((sc1d & 0x05) == 0x05)
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goto somebody_else;
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else if ((sc1d & 0x04) == 0x04)
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return (dma_stat & 4) == 4;
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}
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somebody_else:
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return (dma_stat & 4) == 4; /* return 1 if INTR asserted */
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}
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static void pdc202xx_dma_lost_irq(ide_drive_t *drive)
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{
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ide_hwif_t *hwif = HWIF(drive);
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if (hwif->resetproc != NULL)
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hwif->resetproc(drive);
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ide_dma_lost_irq(drive);
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}
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static void pdc202xx_dma_timeout(ide_drive_t *drive)
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{
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ide_hwif_t *hwif = HWIF(drive);
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if (hwif->resetproc != NULL)
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hwif->resetproc(drive);
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ide_dma_timeout(drive);
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}
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static void pdc202xx_reset_host (ide_hwif_t *hwif)
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{
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unsigned long high_16 = hwif->dma_master;
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u8 udma_speed_flag = inb(high_16 | 0x001f);
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outb(udma_speed_flag | 0x10, high_16 | 0x001f);
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mdelay(100);
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outb(udma_speed_flag & ~0x10, high_16 | 0x001f);
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mdelay(2000); /* 2 seconds ?! */
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printk(KERN_WARNING "PDC202XX: %s channel reset.\n",
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hwif->channel ? "Secondary" : "Primary");
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}
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static void pdc202xx_reset (ide_drive_t *drive)
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{
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ide_hwif_t *hwif = HWIF(drive);
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ide_hwif_t *mate = hwif->mate;
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pdc202xx_reset_host(hwif);
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pdc202xx_reset_host(mate);
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ide_set_max_pio(drive);
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}
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static unsigned int __devinit init_chipset_pdc202xx(struct pci_dev *dev,
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const char *name)
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{
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return dev->irq;
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}
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static void __devinit init_hwif_pdc202xx(ide_hwif_t *hwif)
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{
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struct pci_dev *dev = hwif->pci_dev;
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/* PDC20265 has problems with large LBA48 requests */
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if ((dev->device == PCI_DEVICE_ID_PROMISE_20267) ||
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(dev->device == PCI_DEVICE_ID_PROMISE_20265))
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hwif->rqsize = 256;
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hwif->set_pio_mode = &pdc202xx_set_pio_mode;
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hwif->set_dma_mode = &pdc202xx_set_mode;
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hwif->quirkproc = &pdc202xx_quirkproc;
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if (hwif->pci_dev->device != PCI_DEVICE_ID_PROMISE_20246)
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hwif->resetproc = &pdc202xx_reset;
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hwif->err_stops_fifo = 1;
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hwif->drives[0].autotune = hwif->drives[1].autotune = 1;
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if (hwif->dma_base == 0)
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return;
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hwif->dma_lost_irq = &pdc202xx_dma_lost_irq;
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hwif->dma_timeout = &pdc202xx_dma_timeout;
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if (hwif->pci_dev->device != PCI_DEVICE_ID_PROMISE_20246) {
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if (hwif->cbl != ATA_CBL_PATA40_SHORT)
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hwif->cbl = pdc202xx_old_cable_detect(hwif);
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hwif->dma_start = &pdc202xx_old_ide_dma_start;
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hwif->ide_dma_end = &pdc202xx_old_ide_dma_end;
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}
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hwif->ide_dma_test_irq = &pdc202xx_old_ide_dma_test_irq;
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}
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static void __devinit init_dma_pdc202xx(ide_hwif_t *hwif, unsigned long dmabase)
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{
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u8 udma_speed_flag = 0, primary_mode = 0, secondary_mode = 0;
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if (hwif->channel) {
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ide_setup_dma(hwif, dmabase, 8);
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return;
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}
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udma_speed_flag = inb(dmabase | 0x1f);
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primary_mode = inb(dmabase | 0x1a);
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secondary_mode = inb(dmabase | 0x1b);
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printk(KERN_INFO "%s: (U)DMA Burst Bit %sABLED " \
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"Primary %s Mode " \
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"Secondary %s Mode.\n", hwif->cds->name,
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(udma_speed_flag & 1) ? "EN" : "DIS",
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(primary_mode & 1) ? "MASTER" : "PCI",
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(secondary_mode & 1) ? "MASTER" : "PCI" );
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#ifdef CONFIG_PDC202XX_BURST
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if (!(udma_speed_flag & 1)) {
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printk(KERN_INFO "%s: FORCING BURST BIT 0x%02x->0x%02x ",
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hwif->cds->name, udma_speed_flag,
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(udma_speed_flag|1));
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outb(udma_speed_flag | 1, dmabase | 0x1f);
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printk("%sACTIVE\n", (inb(dmabase | 0x1f) & 1) ? "" : "IN");
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}
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#endif /* CONFIG_PDC202XX_BURST */
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ide_setup_dma(hwif, dmabase, 8);
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}
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static int __devinit init_setup_pdc202ata4(struct pci_dev *dev,
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ide_pci_device_t *d)
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{
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if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE) {
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u8 irq = 0, irq2 = 0;
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pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
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/* 0xbc */
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pci_read_config_byte(dev, (PCI_INTERRUPT_LINE)|0x80, &irq2);
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if (irq != irq2) {
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pci_write_config_byte(dev,
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(PCI_INTERRUPT_LINE)|0x80, irq); /* 0xbc */
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printk(KERN_INFO "%s: pci-config space interrupt "
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"mirror fixed.\n", d->name);
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}
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}
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return ide_setup_pci_device(dev, d);
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}
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static int __devinit init_setup_pdc20265(struct pci_dev *dev,
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ide_pci_device_t *d)
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{
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if ((dev->bus->self) &&
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(dev->bus->self->vendor == PCI_VENDOR_ID_INTEL) &&
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((dev->bus->self->device == PCI_DEVICE_ID_INTEL_I960) ||
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(dev->bus->self->device == PCI_DEVICE_ID_INTEL_I960RM))) {
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printk(KERN_INFO "ide: Skipping Promise PDC20265 "
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"attached to I2O RAID controller.\n");
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return -ENODEV;
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}
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return ide_setup_pci_device(dev, d);
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}
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static int __devinit init_setup_pdc202xx(struct pci_dev *dev,
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ide_pci_device_t *d)
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{
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return ide_setup_pci_device(dev, d);
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}
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static ide_pci_device_t pdc202xx_chipsets[] __devinitdata = {
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{ /* 0 */
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.name = "PDC20246",
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.init_setup = init_setup_pdc202ata4,
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.init_chipset = init_chipset_pdc202xx,
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.init_hwif = init_hwif_pdc202xx,
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.init_dma = init_dma_pdc202xx,
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.extra = 16,
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.host_flags = IDE_HFLAG_OFF_BOARD,
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.pio_mask = ATA_PIO4,
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.mwdma_mask = ATA_MWDMA2,
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.udma_mask = ATA_UDMA2,
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},{ /* 1 */
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.name = "PDC20262",
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.init_setup = init_setup_pdc202ata4,
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.init_chipset = init_chipset_pdc202xx,
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.init_hwif = init_hwif_pdc202xx,
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.init_dma = init_dma_pdc202xx,
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.extra = 48,
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.host_flags = IDE_HFLAG_OFF_BOARD,
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.pio_mask = ATA_PIO4,
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.mwdma_mask = ATA_MWDMA2,
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.udma_mask = ATA_UDMA4,
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},{ /* 2 */
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.name = "PDC20263",
|
|
.init_setup = init_setup_pdc202ata4,
|
|
.init_chipset = init_chipset_pdc202xx,
|
|
.init_hwif = init_hwif_pdc202xx,
|
|
.init_dma = init_dma_pdc202xx,
|
|
.extra = 48,
|
|
.host_flags = IDE_HFLAG_OFF_BOARD,
|
|
.pio_mask = ATA_PIO4,
|
|
.mwdma_mask = ATA_MWDMA2,
|
|
.udma_mask = ATA_UDMA4,
|
|
},{ /* 3 */
|
|
.name = "PDC20265",
|
|
.init_setup = init_setup_pdc20265,
|
|
.init_chipset = init_chipset_pdc202xx,
|
|
.init_hwif = init_hwif_pdc202xx,
|
|
.init_dma = init_dma_pdc202xx,
|
|
.extra = 48,
|
|
.host_flags = IDE_HFLAG_OFF_BOARD,
|
|
.pio_mask = ATA_PIO4,
|
|
.mwdma_mask = ATA_MWDMA2,
|
|
.udma_mask = ATA_UDMA5,
|
|
},{ /* 4 */
|
|
.name = "PDC20267",
|
|
.init_setup = init_setup_pdc202xx,
|
|
.init_chipset = init_chipset_pdc202xx,
|
|
.init_hwif = init_hwif_pdc202xx,
|
|
.init_dma = init_dma_pdc202xx,
|
|
.extra = 48,
|
|
.host_flags = IDE_HFLAG_OFF_BOARD,
|
|
.pio_mask = ATA_PIO4,
|
|
.mwdma_mask = ATA_MWDMA2,
|
|
.udma_mask = ATA_UDMA5,
|
|
}
|
|
};
|
|
|
|
/**
|
|
* pdc202xx_init_one - called when a PDC202xx is found
|
|
* @dev: the pdc202xx device
|
|
* @id: the matching pci id
|
|
*
|
|
* Called when the PCI registration layer (or the IDE initialization)
|
|
* finds a device matching our IDE device tables.
|
|
*/
|
|
|
|
static int __devinit pdc202xx_init_one(struct pci_dev *dev, const struct pci_device_id *id)
|
|
{
|
|
ide_pci_device_t *d = &pdc202xx_chipsets[id->driver_data];
|
|
|
|
return d->init_setup(dev, d);
|
|
}
|
|
|
|
static const struct pci_device_id pdc202xx_pci_tbl[] = {
|
|
{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20246), 0 },
|
|
{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20262), 1 },
|
|
{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20263), 2 },
|
|
{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20265), 3 },
|
|
{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20267), 4 },
|
|
{ 0, },
|
|
};
|
|
MODULE_DEVICE_TABLE(pci, pdc202xx_pci_tbl);
|
|
|
|
static struct pci_driver driver = {
|
|
.name = "Promise_Old_IDE",
|
|
.id_table = pdc202xx_pci_tbl,
|
|
.probe = pdc202xx_init_one,
|
|
};
|
|
|
|
static int __init pdc202xx_ide_init(void)
|
|
{
|
|
return ide_pci_register_driver(&driver);
|
|
}
|
|
|
|
module_init(pdc202xx_ide_init);
|
|
|
|
MODULE_AUTHOR("Andre Hedrick, Frank Tiernan");
|
|
MODULE_DESCRIPTION("PCI driver module for older Promise IDE");
|
|
MODULE_LICENSE("GPL");
|