Florian Fainelli 62cedc4fde MIPS: introduce CPU_R4K_CACHE_TLB ... R4K-style CPUs having common code to support their caches and tlb have this boolean defined by default. Allows us to remove some lines in arch/mips/mm/Makefile. Signed-off-by: Florian Fainelli <florian@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/3328/ Signed-off-by: John Crispin <blogic@openwrt.org>		2012-08-22 23:46:38 +02:00
..
c-octeon.c	MIPS: Octeon: Use board_cache_error_setup for cache error handler setup.	2012-05-16 23:34:33 +02:00
c-r3k.c
c-r4k.c	MIPS: Fix decoding of c0_config1 for MIPSxx caches with 32 ways per set.	2012-07-19 11:23:43 +02:00
c-tx39.c
cache.c
cerr-sb1.c
cex-gen.S
cex-oct.S
cex-sb1.S
dma-default.c
extable.c
fault.c
gup.c
highmem.c
hugetlbpage.c
init.c
ioremap.c
Makefile	MIPS: introduce CPU_R4K_CACHE_TLB	2012-08-22 23:46:38 +02:00
mmap.c
page-funcs.S	MIPS: Refactor 'clear_page' and 'copy_page' functions.	2012-07-19 11:23:43 +02:00
page.c	MIPS: Refactor 'clear_page' and 'copy_page' functions.	2012-07-19 11:23:43 +02:00
pgtable-32.c
pgtable-64.c
sc-ip22.c
sc-mips.c
sc-r5k.c
sc-rm7k.c
tlb-r3k.c
tlb-r4k.c
tlb-r8k.c
tlbex-fault.S
tlbex.c	MIPS: Add support for the M14Kc core.	2012-07-06 23:56:00 +02:00
uasm.c	MIPS: Fixup ordering of micro assembler instructions.	2012-07-23 13:55:56 +01:00