forked from luck/tmp_suning_uos_patched
65d7d94405
- The mxs wdog is implemented in RTC block. - There is a generic software reset routine for most modules on mxs. Signed-off-by: Shawn Guo <shawn.guo@freescale.com> Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
138 lines
3.3 KiB
C
138 lines
3.3 KiB
C
/*
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* Copyright (C) 1999 ARM Limited
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* Copyright (C) 2000 Deep Blue Solutions Ltd
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* Copyright 2006-2007,2010 Freescale Semiconductor, Inc. All Rights Reserved.
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* Copyright 2008 Juergen Beisert, kernel@pengutronix.de
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* Copyright 2009 Ilya Yanok, Emcraft Systems Ltd, yanok@emcraft.com
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/kernel.h>
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <linux/err.h>
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#include <linux/delay.h>
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#include <linux/init.h>
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#include <asm/proc-fns.h>
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#include <asm/system.h>
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#include <mach/mxs.h>
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#include <mach/common.h>
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#define MX23_CLKCTRL_RESET_OFFSET 0x120
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#define MX28_CLKCTRL_RESET_OFFSET 0x1e0
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#define MXS_CLKCTRL_RESET_CHIP (1 << 1)
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#define MXS_MODULE_CLKGATE (1 << 30)
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#define MXS_MODULE_SFTRST (1 << 31)
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static void __iomem *mxs_clkctrl_reset_addr;
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/*
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* Reset the system. It is called by machine_restart().
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*/
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void arch_reset(char mode, const char *cmd)
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{
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/* reset the chip */
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__mxs_setl(MXS_CLKCTRL_RESET_CHIP, mxs_clkctrl_reset_addr);
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pr_err("Failed to assert the chip reset\n");
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/* Delay to allow the serial port to show the message */
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mdelay(50);
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/* We'll take a jump through zero as a poor second */
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cpu_reset(0);
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}
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static int __init mxs_arch_reset_init(void)
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{
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struct clk *clk;
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mxs_clkctrl_reset_addr = MXS_IO_ADDRESS(MXS_CLKCTRL_BASE_ADDR) +
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(cpu_is_mx23() ? MX23_CLKCTRL_RESET_OFFSET :
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MX28_CLKCTRL_RESET_OFFSET);
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clk = clk_get_sys("rtc", NULL);
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if (!IS_ERR(clk))
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clk_enable(clk);
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return 0;
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}
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core_initcall(mxs_arch_reset_init);
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/*
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* Clear the bit and poll it cleared. This is usually called with
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* a reset address and mask being either SFTRST(bit 31) or CLKGATE
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* (bit 30).
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*/
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static int clear_poll_bit(void __iomem *addr, u32 mask)
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{
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int timeout = 0x400;
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/* clear the bit */
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__mxs_clrl(mask, addr);
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/*
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* SFTRST needs 3 GPMI clocks to settle, the reference manual
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* recommends to wait 1us.
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*/
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udelay(1);
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/* poll the bit becoming clear */
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while ((__raw_readl(addr) & mask) && --timeout)
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/* nothing */;
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return !timeout;
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}
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int mxs_reset_block(void __iomem *reset_addr)
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{
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int ret;
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int timeout = 0x400;
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/* clear and poll SFTRST */
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ret = clear_poll_bit(reset_addr, MXS_MODULE_SFTRST);
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if (unlikely(ret))
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goto error;
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/* clear CLKGATE */
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__mxs_clrl(MXS_MODULE_CLKGATE, reset_addr);
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/* set SFTRST to reset the block */
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__mxs_setl(MXS_MODULE_SFTRST, reset_addr);
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udelay(1);
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/* poll CLKGATE becoming set */
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while ((!(__raw_readl(reset_addr) & MXS_MODULE_CLKGATE)) && --timeout)
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/* nothing */;
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if (unlikely(!timeout))
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goto error;
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/* clear and poll SFTRST */
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ret = clear_poll_bit(reset_addr, MXS_MODULE_SFTRST);
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if (unlikely(ret))
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goto error;
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/* clear and poll CLKGATE */
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ret = clear_poll_bit(reset_addr, MXS_MODULE_CLKGATE);
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if (unlikely(ret))
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goto error;
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return 0;
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error:
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pr_err("%s(%p): module reset timeout\n", __func__, reset_addr);
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return -ETIMEDOUT;
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}
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