forked from luck/tmp_suning_uos_patched
171 lines
8.0 KiB
C
171 lines
8.0 KiB
C
#ifndef _SK_MCA_INCLUDE_
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#define _SK_MCA_INCLUDE_
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#ifdef _SK_MCA_DRIVER_
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/* Adapter ID's */
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#define SKNET_MCA_ID 0x6afd
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#define SKNET_JUNIOR_MCA_ID 0x6be9
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/* media enumeration - defined in a way that it fits onto the MC2+'s
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POS registers... */
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typedef enum { Media_10Base2, Media_10BaseT,
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Media_10Base5, Media_Unknown, Media_Count
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} skmca_medium;
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/* private structure */
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typedef struct {
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unsigned int slot; /* MCA-Slot-# */
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void __iomem *base;
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void __iomem *macbase; /* base address of MAC address PROM */
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void __iomem *ioregaddr;/* address of I/O-register (Lo) */
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void __iomem *ctrladdr; /* address of control/stat register */
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void __iomem *cmdaddr; /* address of I/O-command register */
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int nextrx; /* index of next RX descriptor to
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be read */
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int nexttxput; /* index of next free TX descriptor */
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int nexttxdone; /* index of next TX descriptor to
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be finished */
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int txbusy; /* # of busy TX descriptors */
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struct net_device_stats stat; /* packet statistics */
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int realirq; /* memorizes actual IRQ, even when
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currently not allocated */
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skmca_medium medium; /* physical cannector */
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spinlock_t lock;
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} skmca_priv;
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/* card registers: control/status register bits */
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#define CTRL_ADR_DATA 0 /* Bit 0 = 0 ->access data register */
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#define CTRL_ADR_RAP 1 /* Bit 0 = 1 ->access RAP register */
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#define CTRL_RW_WRITE 0 /* Bit 1 = 0 ->write register */
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#define CTRL_RW_READ 2 /* Bit 1 = 1 ->read register */
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#define CTRL_RESET_ON 0 /* Bit 3 = 0 ->reset board */
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#define CTRL_RESET_OFF 8 /* Bit 3 = 1 ->no reset of board */
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#define STAT_ADR_DATA 0 /* Bit 0 of ctrl register read back */
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#define STAT_ADR_RAP 1
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#define STAT_RW_WRITE 0 /* Bit 1 of ctrl register read back */
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#define STAT_RW_READ 2
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#define STAT_RESET_ON 0 /* Bit 3 of ctrl register read back */
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#define STAT_RESET_OFF 8
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#define STAT_IRQ_ACT 0 /* interrupt pending */
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#define STAT_IRQ_NOACT 16 /* no interrupt pending */
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#define STAT_IO_NOBUSY 0 /* no transfer busy */
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#define STAT_IO_BUSY 32 /* transfer busy */
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/* I/O command register bits */
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#define IOCMD_GO 128 /* Bit 7 = 1 -> start register xfer */
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/* LANCE registers */
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#define LANCE_CSR0 0 /* Status/Control */
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#define CSR0_ERR 0x8000 /* general error flag */
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#define CSR0_BABL 0x4000 /* transmitter timeout */
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#define CSR0_CERR 0x2000 /* collision error */
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#define CSR0_MISS 0x1000 /* lost Rx block */
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#define CSR0_MERR 0x0800 /* memory access error */
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#define CSR0_RINT 0x0400 /* receiver interrupt */
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#define CSR0_TINT 0x0200 /* transmitter interrupt */
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#define CSR0_IDON 0x0100 /* initialization done */
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#define CSR0_INTR 0x0080 /* general interrupt flag */
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#define CSR0_INEA 0x0040 /* interrupt enable */
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#define CSR0_RXON 0x0020 /* receiver enabled */
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#define CSR0_TXON 0x0010 /* transmitter enabled */
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#define CSR0_TDMD 0x0008 /* force transmission now */
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#define CSR0_STOP 0x0004 /* stop LANCE */
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#define CSR0_STRT 0x0002 /* start LANCE */
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#define CSR0_INIT 0x0001 /* read initialization block */
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#define LANCE_CSR1 1 /* addr bit 0..15 of initialization */
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#define LANCE_CSR2 2 /* 16..23 block */
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#define LANCE_CSR3 3 /* Bus control */
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#define CSR3_BCON_HOLD 0 /* Bit 0 = 0 -> BM1,BM0,HOLD */
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#define CSR3_BCON_BUSRQ 1 /* Bit 0 = 1 -> BUSAK0,BYTE,BUSRQ */
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#define CSR3_ALE_HIGH 0 /* Bit 1 = 0 -> ALE asserted high */
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#define CSR3_ALE_LOW 2 /* Bit 1 = 1 -> ALE asserted low */
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#define CSR3_BSWAP_OFF 0 /* Bit 2 = 0 -> no byte swap */
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#define CSR3_BSWAP_ON 4 /* Bit 2 = 1 -> byte swap */
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/* LANCE structures */
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typedef struct { /* LANCE initialization block */
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u16 Mode; /* mode flags */
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u8 PAdr[6]; /* MAC address */
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u8 LAdrF[8]; /* Multicast filter */
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u32 RdrP; /* Receive descriptor */
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u32 TdrP; /* Transmit descriptor */
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} LANCE_InitBlock;
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/* Mode flags init block */
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#define LANCE_INIT_PROM 0x8000 /* enable promiscous mode */
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#define LANCE_INIT_INTL 0x0040 /* internal loopback */
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#define LANCE_INIT_DRTY 0x0020 /* disable retry */
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#define LANCE_INIT_COLL 0x0010 /* force collision */
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#define LANCE_INIT_DTCR 0x0008 /* disable transmit CRC */
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#define LANCE_INIT_LOOP 0x0004 /* loopback */
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#define LANCE_INIT_DTX 0x0002 /* disable transmitter */
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#define LANCE_INIT_DRX 0x0001 /* disable receiver */
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typedef struct { /* LANCE Tx descriptor */
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u16 LowAddr; /* bit 0..15 of address */
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u16 Flags; /* bit 16..23 of address + Flags */
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u16 Len; /* 2s complement of packet length */
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u16 Status; /* Result of transmission */
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} LANCE_TxDescr;
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#define TXDSCR_FLAGS_OWN 0x8000 /* LANCE owns descriptor */
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#define TXDSCR_FLAGS_ERR 0x4000 /* summary error flag */
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#define TXDSCR_FLAGS_MORE 0x1000 /* more than one retry needed? */
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#define TXDSCR_FLAGS_ONE 0x0800 /* one retry? */
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#define TXDSCR_FLAGS_DEF 0x0400 /* transmission deferred? */
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#define TXDSCR_FLAGS_STP 0x0200 /* first packet in chain? */
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#define TXDSCR_FLAGS_ENP 0x0100 /* last packet in chain? */
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#define TXDSCR_STATUS_BUFF 0x8000 /* buffer error? */
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#define TXDSCR_STATUS_UFLO 0x4000 /* silo underflow during transmit? */
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#define TXDSCR_STATUS_LCOL 0x1000 /* late collision? */
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#define TXDSCR_STATUS_LCAR 0x0800 /* loss of carrier? */
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#define TXDSCR_STATUS_RTRY 0x0400 /* retry error? */
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typedef struct { /* LANCE Rx descriptor */
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u16 LowAddr; /* bit 0..15 of address */
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u16 Flags; /* bit 16..23 of address + Flags */
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u16 MaxLen; /* 2s complement of buffer length */
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u16 Len; /* packet length */
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} LANCE_RxDescr;
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#define RXDSCR_FLAGS_OWN 0x8000 /* LANCE owns descriptor */
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#define RXDSCR_FLAGS_ERR 0x4000 /* summary error flag */
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#define RXDSCR_FLAGS_FRAM 0x2000 /* framing error flag */
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#define RXDSCR_FLAGS_OFLO 0x1000 /* FIFO overflow? */
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#define RXDSCR_FLAGS_CRC 0x0800 /* CRC error? */
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#define RXDSCR_FLAGS_BUFF 0x0400 /* buffer error? */
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#define RXDSCR_FLAGS_STP 0x0200 /* first packet in chain? */
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#define RXDCSR_FLAGS_ENP 0x0100 /* last packet in chain? */
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/* RAM layout */
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#define TXCOUNT 4 /* length of TX descriptor queue */
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#define LTXCOUNT 2 /* log2 of it */
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#define RXCOUNT 4 /* length of RX descriptor queue */
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#define LRXCOUNT 2 /* log2 of it */
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#define RAM_INITBASE 0 /* LANCE init block */
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#define RAM_TXBASE 24 /* Start of TX descriptor queue */
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#define RAM_RXBASE \
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(RAM_TXBASE + (TXCOUNT * 8)) /* Start of RX descriptor queue */
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#define RAM_DATABASE \
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(RAM_RXBASE + (RXCOUNT * 8)) /* Start of data area for frames */
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#define RAM_BUFSIZE 1580 /* max. frame size - should never be
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reached */
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#endif /* _SK_MCA_DRIVER_ */
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#endif /* _SK_MCA_INCLUDE_ */
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