forked from luck/tmp_suning_uos_patched
247055aa21
This patch removes the domain switching functionality via the set_fs and __switch_to functions on cores that have a TLS register. Currently, the ioremap and vmalloc areas share the same level 1 page tables and therefore have the same domain (DOMAIN_KERNEL). When the kernel domain is modified from Client to Manager (via the __set_fs or in the __switch_to function), the XN (eXecute Never) bit is overridden and newer CPUs can speculatively prefetch the ioremap'ed memory. Linux performs the kernel domain switching to allow user-specific functions (copy_to/from_user, get/put_user etc.) to access kernel memory. In order for these functions to work with the kernel domain set to Client, the patch modifies the LDRT/STRT and related instructions to the LDR/STR ones. The user pages access rights are also modified for kernel read-only access rather than read/write so that the copy-on-write mechanism still works. CPU_USE_DOMAINS gets disabled only if the hardware has a TLS register (CPU_32v6K is defined) since writing the TLS value to the high vectors page isn't possible. The user addresses passed to the kernel are checked by the access_ok() function so that they do not point to the kernel space. Tested-by: Anton Vorontsov <cbouatmailru@gmail.com> Cc: Tony Lindgren <tony@atomide.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
127 lines
3.1 KiB
C
127 lines
3.1 KiB
C
#ifndef _ASM_ARM_FUTEX_H
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#define _ASM_ARM_FUTEX_H
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#ifdef __KERNEL__
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#ifdef CONFIG_SMP
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#include <asm-generic/futex.h>
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#else /* !SMP, we can work around lack of atomic ops by disabling preemption */
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#include <linux/futex.h>
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#include <linux/preempt.h>
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#include <linux/uaccess.h>
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#include <asm/errno.h>
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#include <asm/domain.h>
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#define __futex_atomic_op(insn, ret, oldval, uaddr, oparg) \
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__asm__ __volatile__( \
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"1: " T(ldr) " %1, [%2]\n" \
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" " insn "\n" \
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"2: " T(str) " %0, [%2]\n" \
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" mov %0, #0\n" \
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"3:\n" \
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" .pushsection __ex_table,\"a\"\n" \
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" .align 3\n" \
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" .long 1b, 4f, 2b, 4f\n" \
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" .popsection\n" \
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" .pushsection .fixup,\"ax\"\n" \
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"4: mov %0, %4\n" \
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" b 3b\n" \
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" .popsection" \
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: "=&r" (ret), "=&r" (oldval) \
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: "r" (uaddr), "r" (oparg), "Ir" (-EFAULT) \
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: "cc", "memory")
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static inline int
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futex_atomic_op_inuser (int encoded_op, int __user *uaddr)
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{
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int op = (encoded_op >> 28) & 7;
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int cmp = (encoded_op >> 24) & 15;
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int oparg = (encoded_op << 8) >> 20;
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int cmparg = (encoded_op << 20) >> 20;
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int oldval = 0, ret;
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if (encoded_op & (FUTEX_OP_OPARG_SHIFT << 28))
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oparg = 1 << oparg;
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if (!access_ok(VERIFY_WRITE, uaddr, sizeof(int)))
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return -EFAULT;
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pagefault_disable(); /* implies preempt_disable() */
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switch (op) {
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case FUTEX_OP_SET:
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__futex_atomic_op("mov %0, %3", ret, oldval, uaddr, oparg);
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break;
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case FUTEX_OP_ADD:
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__futex_atomic_op("add %0, %1, %3", ret, oldval, uaddr, oparg);
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break;
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case FUTEX_OP_OR:
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__futex_atomic_op("orr %0, %1, %3", ret, oldval, uaddr, oparg);
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break;
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case FUTEX_OP_ANDN:
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__futex_atomic_op("and %0, %1, %3", ret, oldval, uaddr, ~oparg);
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break;
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case FUTEX_OP_XOR:
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__futex_atomic_op("eor %0, %1, %3", ret, oldval, uaddr, oparg);
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break;
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default:
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ret = -ENOSYS;
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}
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pagefault_enable(); /* subsumes preempt_enable() */
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if (!ret) {
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switch (cmp) {
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case FUTEX_OP_CMP_EQ: ret = (oldval == cmparg); break;
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case FUTEX_OP_CMP_NE: ret = (oldval != cmparg); break;
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case FUTEX_OP_CMP_LT: ret = (oldval < cmparg); break;
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case FUTEX_OP_CMP_GE: ret = (oldval >= cmparg); break;
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case FUTEX_OP_CMP_LE: ret = (oldval <= cmparg); break;
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case FUTEX_OP_CMP_GT: ret = (oldval > cmparg); break;
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default: ret = -ENOSYS;
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}
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}
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return ret;
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}
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static inline int
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futex_atomic_cmpxchg_inatomic(int __user *uaddr, int oldval, int newval)
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{
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int val;
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if (!access_ok(VERIFY_WRITE, uaddr, sizeof(int)))
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return -EFAULT;
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pagefault_disable(); /* implies preempt_disable() */
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__asm__ __volatile__("@futex_atomic_cmpxchg_inatomic\n"
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"1: " T(ldr) " %0, [%3]\n"
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" teq %0, %1\n"
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" it eq @ explicit IT needed for the 2b label\n"
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"2: " T(streq) " %2, [%3]\n"
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"3:\n"
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" .pushsection __ex_table,\"a\"\n"
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" .align 3\n"
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" .long 1b, 4f, 2b, 4f\n"
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" .popsection\n"
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" .pushsection .fixup,\"ax\"\n"
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"4: mov %0, %4\n"
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" b 3b\n"
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" .popsection"
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: "=&r" (val)
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: "r" (oldval), "r" (newval), "r" (uaddr), "Ir" (-EFAULT)
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: "cc", "memory");
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pagefault_enable(); /* subsumes preempt_enable() */
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return val;
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}
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#endif /* !SMP */
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#endif /* __KERNEL__ */
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#endif /* _ASM_ARM_FUTEX_H */
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