AcoSail/kernel_optimize_test
8
0
Fork 0
forked from luck/tmp_suning_uos_patched
Code Pull Requests Activity
67b35e5d01
kernel_optimize_test/arch/mips/power
History
Ralf Baechle 44eeab6741 MIPS: Hibernation: Remove SMP TLB and cacheflushing code. 
We can't perform any flushes on SMP from swsusp_arch_resume because
interrupts are disabled.  A cross-CPU flush is unnecessary anyway
because all but the local CPU have already been disabled.  A local
flush is not needed either because we didn't change any mappings.  So
just delete the code.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-06-24 18:34:39 +01:00
..
cpu.c
hibernate.S MIPS: Hibernation: Remove SMP TLB and cacheflushing code. 2009-06-24 18:34:39 +01:00
Makefile